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Simulators >> Circuit Simulators >> Stability analysis for multiple feedback loops
https://designers-guide.org/forum/YaBB.pl?num=1255588493

Message started by bharat on Oct 14^th, 2009, 11:34pm

Title: Stability analysis for multiple feedback loops
Post by bharat on Oct 14^th, 2009, 11:34pm

If there are more than one feedback loop in any circuit ( voltage regulator); to check the stability should one break all the loops and check for stability OR the loop having highest loop gain (A*beta)
will have potential stability threat, if the circuit is safe there, other feedback loops may not be as significant.

In other words, having more than feedback loop is bad design, because optimising the circuit for all the three loops (say) to be stable is difficult task.

Regards

Title: Re: Stability analysis for multiple feedback loops
Post by Frank Wiedmann on Oct 15^th, 2009, 1:19am

See http://www.designers-guide.org/Forum/YaBB.pl?num=1163532257 and http://www.designers-guide.org/Forum/YaBB.pl?num=1217822985.

Title: Re: Stability analysis for multiple feedback loops
Post by thechopper on Oct 16^th, 2009, 10:29am

this one also might be useful http://www.designers-guide.org/Forum/YaBB.pl?num=1198131494

Best
Tosei

Title: Re: Stability analysis for multiple feedback loops
Post by buddypoor on Oct 17^th, 2009, 1:52am

HdrChopper wrote on Oct 16^th, 2009, 10:29am:

this one also might be useful http://www.designers-guide.org/Forum/YaBB.pl?num=1198131494
Best
Tosei

Yes, Tosei. Thanks for pointing the attention of bharat to this rather deep discussion of the subject. I think, if there are no new arguments everything has been said regarding the original question.
Thanks
Lutz

Title: Re: Stability analysis for multiple feedback loops
Post by bharat on Oct 24^th, 2009, 7:44am

Thanks to Frank, Tosei and Lutz for the pointers and comments.
Looks like much has been discussed on the topic ..

I have gathered that most of the posts were devoted to where to break the loop vs advantages of not breaking the loop. I agree 'stb' analysis is convenient over classical breaking the loop method.
I would have been agreed before seeing the interesting behavior ..
I am working on voltage regulator which has traditional 2 stage op-amp followed by CS PMOS third stage.
I have 3 potential place where I can break the loop. At O/P of 1st stage, at O/P of 2nd stage and I/P of 1st stage diff pair.
Theoretically I should get the same DC loop gain but I am seeing different loop gains. The obvious reason is that DC op points are not same while doing 'stb' analysis.
Frank, will you comment.

Thanks

Title: Re: Stability analysis for multiple feedback loops
Post by bharat on Oct 24^th, 2009, 8:44am

...contd.

attaching the ckt.

Title: Re: Stability analysis for multiple feedback loops
Post by buddypoor on Oct 24^th, 2009, 9:35am

My recommendation is to open the loop at X3 and to place an AC voltage source of 1V BETWEEN both nodes (left and right of the break point).
Thus, the dc loop and, hence, the operating point remains unchainged.
The ac loop gain then is simply the ratio of both node voltages.
This is a modified MIDLLEBROOK method and it works always - as long as there is no severe load change at the point chosen to insert the voltage source.

Title: Re: Stability analysis for multiple feedback loops
Post by bharat on Oct 24^th, 2009, 9:51am

buddypoor, thanks

what you suggested is always recommended. I did the same and got the PM and GM in the specified limit. To add the surprise while doing the transient analysis of load current at the regulator output, the output started ringing. This behavior was against the PM and GM of AC/STB analysis.
This forced to analyse the circuit further and we found that while breaking the loop at X2, GM was poor and gain plot was corssing the 0dB twice and the loop was unstable.
This analysis matches to my load current transient response.
I am rephrasing my questions again;
1) while breaking the loop (stb analysis) at X1, X2 and X3 the DC loop gain should be same, but I am seeing the difference of 5-7 dB.
This suggests that stb analysis is not perfect and it is hard to mimic the ckt with zero source impedance and infinite load impedance of AC source. (not sure though)
2) If the ckt is stable at X3 doesn't ensure that ckt. would be stable at X2 and X1 too.

Thanks

Title: Re: Stability analysis for multiple feedback loops
Post by buddypoor on Oct 24^th, 2009, 10:50am

Hi BHARAT,

As far as I can see, you only have one loop and in principle it does not matter at which point (X1, X2 or X3) you are going to measure/simulate the loop gain.
However, when you don´t intent to simulate the load separately which is disconnected by introducing the ac source , you have to select a point where a small output resistance looks into a high resistance - and that´s X3.
I know, that there will remain a small error (because of non-ideal load conditions), but I think it will be acceptable.
But I must confess that I am not familiar with the STB analysis (I use PSpice and similar packages), but I am sure that the PM and GM at X2 and X3 (if properly determined !!) will be identical to the values at X3.
Because it is the same loop !
Another problem may be: The concept of PM and GM is applicable not to all feedback systems but only to those systems which allow the simplified Nyquist criterion (stable open loop system and no zeros in the RHP and only one loop gain crossing of the 0 dB-line).
Did you check this?
Regards

Title: Re: Stability analysis for multiple feedback loops
Post by Frank Wiedmann on Oct 26^th, 2009, 2:43am

There are two possible reasons why the transient behavior does not match the results of the stb analysis:

There is more than one loop in the circuit and the stb probe is not part of all of the loops.
There is a significant part of the signal that bypasses the loop. See the section about Middlebrook's General Feedback Theorem from my webpage http://sites.google.com/site/frankwiedmann/loopgain.

In case of doubt, always use transient analysis to see the real circuit behavior.

Title: Re: Stability analysis for multiple feedback loops
Post by thechopper on Oct 26^th, 2009, 4:56am

bharat wrote on Oct 24^th, 2009, 9:51am:

1) while breaking the loop (stb analysis) at X1, X2 and X3 the DC loop gain should be same, but I am seeing the difference of 5-7 dB.
This suggests that stb analysis is not perfect and it is hard to mimic the ckt with zero source impedance and infinite load impedance of AC source. (not sure though)
2) If the ckt is stable at X3 doesn't ensure that ckt. would be stable at X2 and X1 too.

Hi Bharat,

Concerning your first question,: the stb is accurate as long as the hypothesis for applying such analysis are fullfilled. -> in order for the stb analysis to be valid your ckt should be able to be analyzed as a single feedback system This is valid only when:
a) all local feedback loops inside the main loop are individually stable
b) all the invovled loops have a common break point

Your circuit has to fulfill at least one of these two requirements in order to be analyzed as a single loop system (and therefore use stb analysis).

This idea goes along with the lines Frank pointed out in 1) in his post.

As for Frank's second bullet, he is referring to a heavy feedforward component which - in usual feedback theory - is not considered. This might affect the overall stability of your system too.

One more comment: it is usually difficult to mimic the ckt behavior with a zero source and infinite load impendace AC source that breaks the loop, since usually stability is set by the voltage and current feedback loop. Usually with your AC voltage source you only analyise the stability of your voltage feedback loop.
As buddypoor pointed out, the approximation is valid only when the loading effects are negligible, but this method is error-prone. so it is always recommended NOT to break the loop, but rather include your probe inside the loop. Actually the stb analysis is supposed to be more accurate since it consider both loops: voltage and current.

Sorry for the long post

Best
Tosei

Title: Re: Stability analysis for multiple feedback loops
Post by thetan on May 5^th, 2016, 2:03pm

Hello All,

I have been following all the interesting discussions on this forum about multiple loop stability analysis. I am designing a similar LDO as presented in this discussion and I have some doubts about its stability analysis. It would be really great if you folks can help me out.

The block diagram of the designed Reverse nested miller compensation based LDO is shown in the attached figure. I have done the analysis using stb analysis of spectre. I put iprobe first on the red cross, the conventional point of analysis for an LDO. This gives a PM of 90degrees and unity gain frequency of 150KHz. But when I look at the step response shown in figure, the initial response time cannot be directly mapped to this frequency domain analysis. So, I do STB analysis by putting iprobe at the green cross point. This shows UGF of 15MHz and PM of 40degrees which explains the response time.

My question is: We have a rule of thumb of 60degrees PM for CMOS circuits. But how do we define phase and gain margins for multiple loop systems? In the forum discussions on multi-loop analysis, I have seen that everyone talks about stability. But do we have some quantization on the PM and GM numbers for stability of multiple loops? Isn't taking PM= 60degrees rule of thumb for all loops in these kind of systems an over-estimation? If you can suggest some paper/books/reference which discusses this?

Many thanks in advance!

Title: Re: Stability analysis for multiple feedback loops
Post by raja.cedt on May 6^th, 2016, 8:23am

HI-
generally 60-65 is very good number irrespective of number of loops. But you should consider gain margin also other wise there could be small ripple on top of exponential settling. typically 12dB is good gain margin. So I would suggest you to Quote both always. Check fig-35 in the following paper.

http://web.mit.edu/klund/www/papers/ACC04_opcomp.pdf

regarding multi-loops: All the faster loop poles will be non dominate pole for the slow loop, so as long as they are very far from the slow loop UGB system is stable. I didn't under stand http://web.mit.edu/klund/www/papers/ACC04_opcomp.pdf

In generally it's bit hard to find single loop, take miller compensation, through Cgd 2nd stage will have inner loop. take Ahuja compensation, this will have inner loop through current buffer.

Best regards,
Raj.

Title: Re: Stability analysis for multiple feedback loops
Post by thetan on May 9^th, 2016, 12:49am

Hi Raja,

Thanks for your reply. The gain margin when I analyze the slow loop is greater than 12 dB with PM of 90degrees.

Does this mean that the inner loops should also have a PM of 60degrees and GM of 12dB? From the transfer function (TF) derivation, can we not say that analyzing slow loop (red cross point) is a good point for LDO design (as the denominator should not be 0) ? Or are there any conditions under which the inner loops can be simplified to get this TF which are not considered?

Thanks in advance!

Title: Re: Stability analysis for multiple feedback loops
Post by raja.cedt on May 10^th, 2016, 8:42am

Dear thetan-

Does this mean that the inner loops should also have a PM of 60degrees and GM of 12dB?
Unfortunately I am not expert in the stability theory, but I have designed several working multi loop feedback systems and general belief is make sure all loops are having stable nature (60deg PM and 12dB GM) and diff bandwidths means at least 4-5X variation among stages (of course it depends on your power and area budget).

From the transfer function (TF) derivation, can we not say that analyzing slow loop (red cross point) is a good point for LDO design (as the denominator should not be 0)
Yes slow loop determines the overall UGB, But to find overall loop stability you need to break all loops at time, hence you need to break only in the green cross. red cross is the rite one.

The above theory works pretty well in the practice, best example is PLL.
Intersting theory: Control system theory says any composite feedback network with unstable inner loops can be compensated with gain (aka Conditionally stable systems). Example: take a system with RHP poles say 1/(s-10) now keep this insde a simple loop with gain >10 say 20. Overall loop transfer function is 20/(s+10), stable. I have never tried in analogue this, would like to know if any one have experience on this. One problem to implement the above theory in circuits is once a system is unstable bias point will disturb and can't use linear theory any more, but not sure.

Hope this helps,
Raj.

Title: Re: Stability analysis for multiple feedback loops
Post by thetan on May 11^th, 2016, 3:59pm

Hi Raja,

Thanks for your reply. I did not understand your second answer "hence you need to break only in the green cross. red cross is the rite one."

Can you please make this more clear?

Thanks!

Title: Re: Stability analysis for multiple feedback loops
Post by raja.cedt on May 12^th, 2016, 10:14am

Hello-
Sorry I wrote in bit confusing manner. what I am saying is we should break all the loops at a time, hence red is the only one accurate break point.

Best Regards,
Raj.

Title: Re: Stability analysis for multiple feedback loops
Post by thetan on May 13^th, 2016, 12:47am

Hi Raja,

Thanks for your replies and sharing your experience. I agree with you that red cross is a good point indeed as that's the place which shows real closed loop behavior. I saw in few more trials that there can be situations when inner loop (green cross point ) shows bad Phase margins even less than 40degrees. But the fast behavior seen is still the same. Saying that, I mean even if PM > 60 or PM < 40 degrees for the green cross point I don't see much change in transient response.

In the paper you attached, I liked the way gain margin explains the ringing in figure 35. From experiments I see if I increase the gain margin of red cross loop analysis to > 20dB then the transient response becomes smoother. So, may be in this design higher gain margin is a better specification. like >20dB?

Also, one another query was about your explanation of DC biasing getting disturbed with an unstable inner loop. But if this happens should it not appear in the transient response? Arent the models which we use for designing in cadence suppose to show this problem of DC biasing getting disturbed in case of an instablity? or is it something which can only be tested on-chip?

Thanks in advance!