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Design Languages >> Verilog-AMS >> Implementation of Verilog-AMS in AMS Simulator
https://designers-guide.org/forum/YaBB.pl?num=1255597107

Message started by Emmanuele on Oct 15^th, 2009, 1:58am

Title: Implementation of Verilog-AMS in AMS Simulator
Post by Emmanuele on Oct 15^th, 2009, 1:58am

Hi to everybody!
I've just begun learning Verilog-AMS language, and my first concern is the possibility to use the created file in AMS Simulator (in Cadence SPB 16.01).

It's not very clear to me how I can implement a verilogams file in a model; normally I use Design Entry HDL, which theoretically gives the possibility to add parts modeled with Verilog or VHDL.
Nevertheless, I tried to import simple programs (written in a notepad file) using Part Developer, and it gave me plenty of errors.
For example, I tried the first one proposed in the manual:
----------------------------------------------------------
module shiftPlus5(in, out);
input in;
output out;
voltage in, out; //voltage is a signal flow
//discipline compatible with
//electrical, but having a
//potential nature only
analog begin
V(out) <+ 5.0 + V(in);
end
endmodule
----------------------------------------------------------
but I got errors like "Import failed because of an error on line XXX and token 'YYY' in file ZZZ. Correct the input file and reimport."
Any suggestions?

Thank you for the help you'll give me.
Cheers,
Emmanuele

Title: Re: Implementation of Verilog-AMS in AMS Simulator
Post by Frank Wiedmann on Oct 15^th, 2009, 2:49am

Most people in this forum, including myself, are using the Virtuoso IC design software from Cadence and do not have any experience with Cadence SPB.

Title: Re: Implementation of Verilog-AMS in AMS Simulator
Post by Riad KACED on Oct 15^th, 2009, 2:50pm

Hi Emmanuele,

I use the AMS Designer in Virtuoso too.
If you are writing verilog-A (the above code I meant) instead of verilog-AMS, then stick at the Spectre simulator as Spectre compiles verilog-A, not verilog-AMS. This would save your licenses.

Cheers,
Riad.

Title: Re: Implementation of Verilog-AMS in AMS Simulator
Post by Geoffrey_Coram on Oct 20^th, 2009, 5:22am

This looks like the same issue as in this thread:
http://www.designers-guide.org/Forum/YaBB.pl?num=1255439237/9#9

Please read the responses there.