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Design >> Analog Design >> PEX layout post-simulation problem
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Message started by lhlbluesky_lhl on Oct 19^th, 2009, 4:48am

Title: PEX layout post-simulation problem
Post by lhlbluesky_lhl on Oct 19^th, 2009, 4:48am

for my circuit, pre-simulation and post-simulation differ very much(calibre PEX);

for ex: for a buffer (single-ended), pre-simulation: 10 bit resolution,
post-simulation:9 bit resolution or less;
and, for my whole circuit(3 sub-blocks, 1000 transisitors or so), resolution for pre- and post-simulation decreases from 10 bit to 8 bit or less(6 bit for the worst case).

why?

i want to know what is the main affecting factor for the performance decrease?
i check my PEX netlist, i find that parasitic resistor connecting gate ('g') of transistors(m = 10 or more) is relative large(20 ~ 35 ohm), some other parasitic res 10ohm or so, and parasitic capacitor between real used cap(such as C1, C2 in sc-opamp) and gnd! is also relative large(15f~30f), besides, the other parasitic res(<5 ohm) and cap(<2f) all small.

i changed my layout for some wires, but it improves only a little.

can anyone help me that how to find the key wires in layout or key parasitic res and cap for decreasing my circuit performance?
is there some way or method? or some advice or experience?

thanks in advance, expecting your answers. thanks.