The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> Design flow of FLASH ADC
https://designers-guide.org/forum/YaBB.pl?num=1256116794

Message started by VINAY RAO on Oct 21^st, 2009, 2:19am

Title: Design flow of FLASH ADC
Post by VINAY RAO on Oct 21^st, 2009, 2:19am

Can any one reply about the procedure generally followed to design a FLASH ADC??

Title: Re: Design flow of FLASH ADC
Post by Riad KACED on Oct 22^nd, 2009, 12:16pm

Hi Vinay !

This a very generic question.

1. You need the specs for your Flash ADC
2. I don't know whether you are doing this work just to get your chip nicely framed in the hallway of your Uni or to get it really on silicon. In the latter case, you need to choose the right process and technology node that are likely to get your specs realistic. This is a very important point for industrial prodcution. May be not that important for a PHD dissertation.

Well the next steps are pretty much simple:
1. You may then need to have a high level model for your ADC. You can use system level tools like Matlab/simulink or a behavioral model like Verilog-A, Verilog-AMS, etc ...
2. Once you have proved the functionality, you can then tackle the designing of the IC building blocks in a tool like Cadence DFII. You may need a PDK to get your ADC running on a real process as explained above.
All what you need at this stage is puting the right components together, run transitor level simulations ... etc.

I think this is enough to keep you busy for the first couple of years. You may come back afterwards for the rest of the story, i.e. layout, DRCs, LVS, post layout sims ... etc.

Assuming I have understood your question.
As per the ADC flash itself, just look at the books ...

Cheers,
Riad.

Title: Re: Design flow of FLASH ADC
Post by VINAY RAO on Oct 23^rd, 2009, 1:14am

Thank you...but what is PDK?..Behaviour modelling is just to check whether the chosen architecture will work or not rt??..paper work wnt be enough to analyze whether the chosen architecture wil work or not??
How much the results analyzed in layout deviate from that of schematic one? i mean interms of percentage how much it would be in general??

Title: Re: Design flow of FLASH ADC
Post by Riad KACED on Oct 23^rd, 2009, 11:30am

Hi Vinay,

PDK= Process Design Kit. A PDK is actually a set of files and utilities that translates the Process foundry data in order to be used in a design environment like Cadence DFII. a PDK would for example contain the components library for MOS transistors, res, cap .. etc, the BSIM3V3 models cards that Spectre Needs to simulate those transistors, THE DRC files that Calibre needs to check whether you transistors are well layed -out ... etc.

The Behavioral model is what you need to prove your architecture. If someone wants to design a chip and need an ADC then he can pick up your model without waiting ages for you to complete the transistor level. Behavioral modeling is a very good thing to have when starting a design.

The layout is definitely going to introduce some physical effects that you have not the chance to see when simulating the schematics. To cut the long story short, I would say that the 'blue' wires in your schematic are ideal. In layout, a metal track introduces R/L/C parasitics.

I do not want to dive into much more details as I think the above is good enough for you to start with.

Cheers,
Riad.

Title: Re: Design flow of FLASH ADC
Post by Riad KACED on Oct 25^th, 2009, 6:13am

Hi,

i was web hoping this morning and did find something interesting about PDKs:
http://www.cadence.com/Community/blogs/cic/archive/2009/03/31/what-s-all-the-hoopla-with-pdks.aspx

If you have any more questions about PDKs, please create a new post in a more appropriate section of this forum.

Cheers,
Riad.