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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Regulator Question https://designers-guide.org/forum/YaBB.pl?num=1256531028 Message started by raja.cedt on Oct 25th, 2009, 9:23pm |
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Title: Regulator Question Post by raja.cedt on Oct 25th, 2009, 9:23pm hi, when i was reading a novel regulator called "replica compensated supply regulator" i got the following question. in the figure i attached if op amps have different offsets then whats the output? lets assume A1 has 10mv offsets and A2 has 20mv... Thanks, Rajasekhar. |
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Title: Re: Regulator Question Post by Berti on Oct 26th, 2009, 4:35am Your figure shows two unity-gain buffers driving a common output. Can you please give some more details how this "novel" supply regulator should work? Can you please give more details on the paper(?) where this circuit is proposed? Regards |
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Title: Re: Regulator Question Post by thechopper on Oct 26th, 2009, 4:58am Yes, please. Could provide more details on this circuit? I figure out the final output voltage would be 15mv assuming exactly the same output impedance for both opamps. Most probably the loop gain will significantly drop in order to achieve such operating condition. Best Tosei |
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Title: Re: Regulator Question Post by Mayank on Oct 26th, 2009, 6:43am Hi , Isn't this circuit like connecting 700mV to o/p through two identical Unity-Gain Buffer Paths.....Hence, making it similar to a circuit with 700mV connected to o/p through a Single Unity-Gain Buffer But DOUBLE the Drive of the above used opamp Hence if two opamps are exactly identical in all other respects except for different offsets, I think it should settle at avg off (700-10) & (700-20) ie 685 mV Now, the question is, Am I Correct ?? :P thanx, Mayank. |
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Title: Re: Regulator Question Post by raja.cedt on Oct 26th, 2009, 7:37am hi, first thanks for your reply guyes. you can see fig7 in the following paper. Actually i desinged this circuit in office, but that time i didn't get this doubt. so i thought and for this will come through systematic offset. lets say if both are same then both has +5mv,_5mv systematic offset.hemce 685mv(any one agree?). lets if A1 is faster than A2 then what might be the ans. Please download pap from here http://www.sendspace.com/file/l3ev7n Sorry for this complicated question Thanks, rajasekhar. |
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Title: Re: Regulator Question Post by buddypoor on Oct 26th, 2009, 8:21am Hi rajasekhar, may I jump into the discussion ? In Fig. 7 of your paper I see - Two opamp outputs which are ADDED , and - Two OTA outputs which are connected, but no circuits in which two opamp outputs are tied together ! Or am I wrong ? Regards |
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Title: Re: Regulator Question Post by loose-electron on Oct 26th, 2009, 11:56am The circuit does not make sense at the level of analysis shown. Two ideal op-amps (note the word "IDEAL" here) can not be connected together at the output. If they are OTA's thats a different story. If they are non-ideal amplifiers then it can be analyzed at the transistor level to get an answer. This reminds me of the problem where you connect a logic inverters input to its output. At that level of abstraction it can not be analyzed. You need to go down one level, to the transistor level, and then it can be easily figured out. |
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Title: Re: Regulator Question Post by buddypoor on Oct 26th, 2009, 3:23pm Yes, I agree with the above arguments. The circuit with opamps makes no sense. Probably, rajasekhar has mixed opamps with OTAs. |
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Title: Re: Regulator Question Post by thechopper on Oct 26th, 2009, 5:32pm loose-electron wrote on Oct 26th, 2009, 11:56am:
Hi Jerry, I mostly agree with you. However, if we starting point are two (in principle) opamps with different input referred offset, then those two opamps have to be different (since their op point will not be the same) regardless the used topology. Again assuming non-ideal opamps and that the output/input impedances are not very different and finite (they will due to the different internal unbalances) a first order approx will be that the overall offset will be about +15m for one of them and -15 for the other one. If those impedances are significantly different the offset will be split according to such "voltage divider" set by the output impedances. By my point is that from the very first moment it is stated one amp has 10m of input referred offset while the second one has 20mv, then the opamps are not ideal and in principle they could be connected as shown. Best Tosei |
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Title: Re: Regulator Question Post by loose-electron on Oct 26th, 2009, 9:13pm Assumptions are dangerous things to make in the engineering business. I agree that if assumptions are mad you can get to all kinds of interesting conclusions. I think the original question needs to be re-stated with a bit more detail and perhaps at one level deeper in detail to get anything meaningful. Just for you entertainment - Take a look at the attached schematics. Neither, in my opinion are "well enough defined" to determine whats going on. Two ideal voltage sources can't connect to each other. As well, an inverter, fed back on itself, needs to be defined one level deeper in order to really know whats going on. There are other examples. |
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Title: Re: Regulator Question Post by raja.cedt on Oct 26th, 2009, 9:56pm hi, thanks for your inputs and sorry for for the name opamp instead of OTA. Now can any one assume it is OTA and tell me the ans. @Tosei: hi i didn't understand that impedance division concept? could you please explain more @loose-electron: thanks for your entertainment ckts, regarding 2nd one i don't know ans, every body saying that there is no solution for that. whats your ans? Thanks, rajasekhar. |
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Title: Re: Regulator Question Post by Mayank on Oct 26th, 2009, 9:57pm OTA wire Anding(or o/p short) makes sense because currents can get added up at a node...Two Ideal Voltage Sources on the other hand if connected in parallel will make no sense, until and unless they are non-ideal in which case as buddy said, you can analyse them through their internal resistances (in this case --> o/p res of the opamps) , & as raja said they were identical in all respects except for offsets, 685mV should be the case. But anyways , i dont see any point how this replica scheme acts as voltage regulator. Jerry, Just out of curiosity, If you connect an Inverter's o/p to i/p node & as you said, going one level deeper & Taking into account some propagation delay tau, It will still oscillate right ? [Although i think the waveform will be mostly triangular, coz it wont hv much time to saturate and maintain rail voltages for long] Correct ?? regards, Mayank. |
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Title: Re: Regulator Question Post by raja.cedt on Oct 26th, 2009, 10:02pm hi mayank, it's OTA not Op amp i am sorry for that, inverter connected back to back don't oscillate because at max you will get 90 deg in the loop or otherwise if you think transistor equivalent it will stuck at the trip point of the inverter. Thanks, Rajasekhar. |
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Title: Re: Regulator Question Post by Mayank on Oct 26th, 2009, 10:08pm hi raja, Yeah, i was confused that it will get stuck at the trip point itself...But can you explain why it will get stuck at trip point when it doesnt in the case of 3 inverter chain ?? I mean, there's always a possibility, but like in simulations we give some initial conditions, what if we give some initial condition here also ?? Also, why only 90 degrees phsae shift ?? it's an inverter -- a class AB common source -- should give 180 deg phase shift ?? regards, Mayank. |
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Title: Re: Regulator Question Post by raja.cedt on Oct 26th, 2009, 10:27pm hi Mayank, in case of single stage inverter you will have single cap at the output and there are no other caps so how can you expect more than 90 deg you can refer razaavi ring oscillator section for more clarification and mean while you told it's a class AB stage thats why it has to give 180 deg, i didn't understand this. in case of single inverter you will have one operating point , where as in case of 3 stage oscillator you are correct there is a chance of staying at the trip point but it has enough loop gain, so any noise in the ckt will get you the right output. |
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Title: Re: Regulator Question Post by Mayank on Oct 26th, 2009, 11:07pm Hi, The second circuit, with two ideal Voltage Sources connected See, an Ideal Voltage Source, has ZERO series Resistance, (or ZERO internal resistance of the battery, we can say). If we go into a bit more detail into ckt operation, In a circuit, The current flows from +ve terminal of the battery to the -ve terminal of the battery outside the battery & inside the battery, the current flows from -ve terminal to +ve terminal (which in practical case presents some internal resistance, BUT since we are assuming ideal voltage sources, we say it's ZERO)....So outside the battery, we can consider an Ideal Voltage Source as ZERO series resistance, which maintains 2Vs across it's terminal, & that the Impedance from +ve terminal to -ve Terminal is INFINITE...[Again, dont confuse it with the series resistance, series resistance is modeled in series with +ve terminal to the eff. o/p terminal of the battery, This INFINITE impedance i am talking about is b/w +ve & -ve terminal]. Hence, Assuming that +ve terminal with 2V is shorted to a +ve terminal with 3V voltage wrt common reference GND but both of them are UNCONNECTED to GND. Two cases arise NOW --->> 1. The wire shorting both the terminal is NON-IDEAL : The potential differnce of 1V will drop across the wire resistance in this case, and the two nodes are no longer shorted, but connected with a very small resistance. 2. The wire shorting both the terminals is IDEAL : (which i guess is too much to assume :P , Jerry obviously wont lk this case as it is a pompous assumption :P ) :: Assuming wire is a superconductor with ZERO resistance, Going a bit deeper into superconductor dynamics, We can assume the wire to be a perfectly fluid Electron Gas(Dirac sea of electrons). The two ends of this superconducting wire will have different densities of electrons since their voltages are different. The equilibrium will be achieved through diffusion of e-s in the e- gas from higher density to the lower density. But this is a dynamic phenomena...Finally the voltage across the entire wire will settle at some voltage between 2V & 3V (ideally at 2.5 V)....But In this case, 2.5 V is not forced by some battery, but instead achieved through natural equilibrium process. Sorry for explaining it that extensively...might grow a bit boring to read...But this question perturbed me for years, until i came up with this around 6 months back... Hope it satisfies everyone....I would welcome any additions/corrections/suggestions... I am particularly interested in such wierd kinda basic questions...Wish ppl could ask queries lk this more often...updates my knowledge too :) thanx, Mayank.... |
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Title: Re: Regulator Question Post by raja.cedt on Oct 26th, 2009, 11:32pm hi mayank, first time one person trying to think differently to give ans for this question. thank you. But i didn't understand how different carrier densities at the end because different potential means different electric field, and during equilibrium how voltage will drop? Thanks, rajasekhar. |
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Title: Re: Regulator Question Post by Mayank on Oct 27th, 2009, 12:27am Hi raja, This really should have been a different post altogether... :) i love these type of e- puzzles.....Our reference which we call GND is common for both voltage sources...Now Different Voltages at respective +ve terminals of the battery means there exists an Electric Field between the two potentials remember E = - dV/dX.... Basic assertion ---> Potenial difference means there exists a electric field. But how did the potential generate ?? Because of Charge accumulation...Had there been no difference between the charge density at say two points X1 and X2 .. How will there be any Potential difference between Point X1 and X2 ? The points will be equipotential then....Different Charge densities means different potentials at those points means an electric field which is opposing in nature...will try to equate the charge densities and bring potential to same level.... Am i right ?? --Mayank. |
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Title: Re: Regulator Question Post by Mayank on Oct 27th, 2009, 12:48am Hi again raja, Lemme try to elaborate a bit more...Say you have two ideal voltage sources whose -ve terminals are connected to GND & +ve terminals are hanging as floating(Not connected as of now, No connections, no leakages, no arching nothin...). Then you can assume these points to be ,say, A = 2V + terminal , B = 3V +ve terminal) and assert that these act as POINT CHARGES and have separate electric fields of their own...say k.q1/r2 and k.q2/r2 But force exerted on one due to another will always be same --> k.q1.q2/r2...Since the reference GND wrt which the Potentials of points A and B are different [recollect V = k.q/r], this itself means that the amount of charge present at these nodes is different...So I guess that explains the different charge densities at both the points.. Now, as soon as you connect them through a conductor, The electric field between the two points becomes the -ve gradient of the potential between two points. [It always is the -ve gradient of pot diff b/w 2 points but till the time they were unconnected, we could have argued that individual E fields exist and are differentiable]. Now the E field becomes (3V-2V)/ Length of the conducting wire... But, what if the connecting wire is a superconducter ? ZERO resistance...Perfect e- gas.... Two processes will come into play --> 1> Diffusion process ---> as i explained earlier...Charge carriers e-s diffuse from higher density to lower density -- until dynamic equilibrium is attained...without any external force... 2> E Field b/w two points ---> As soon as you connect the nodes, There will exist a E field between two points which will point from +ve node to -ve node (3V node to 2V node) because of different charge densities at both the points...[remember from prev post..why did E field generate in d 1st place ?? --> coz of diff charge densities.] This E field will cause e-s to move from 3V end to 2V end...reducing E field magnitude in the process..until finally an equilibrium is attained when both potentials become equal... Both there processes will ensure that the superconducting wire...will essentially settle at a common voltage...(ultimately making both the points appear as SHORTED)...But what makes them a SHORT ?? --> These two processes.... If the wire has a finite resistance...Then also initally there will be a voltage drop across the wire...But eventually, both the ends will settle to same voltage levels, because of the above mentioned processes...Differnece being that In this case, the diffusion process will be confronted by the finite resistance of the wire... Hope that explains it all....Still welcoming suggestions....These are ultra-basic topics involving physics...any1 can be wrong anytime :P Anyways, Did this help raja or made it even more confusing :D ? cheers, Mayank.... |
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Title: Re: Regulator Question Post by raja.cedt on Oct 27th, 2009, 2:16am hi mayank, thanks for lot of effort to make me happy through the whole discussion. i understand like this. different potentials means different Charge Density, so when you connected through super conductor charge will transfer through material. so in case of wire with resistance this drop will be across the wire and potentials will be same, but in our present case potential will change. so if any thing wrong in let me know. @mayank: hi man ..i have some other basic doubt in capacitors, if you give your mail id i will post that question..i don't to disturb many people. Thanks, rajasekhar. |
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Title: Re: Regulator Question Post by Mayank on Oct 27th, 2009, 4:19am Hi , Great... :) mail me at singhmayank19@gmail.com...Anyways, raja...i was just curious what's cedt -- name of some organisation ?? You working in industry / academics ? As per your reply, In superconducting case...It's correct..atleast according to me...In normal resistance wire...Only Initially Potential difference will exist...I will try to explain in the mail itself... :) regards, Mayank. |
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Title: Re: Regulator Question Post by loose-electron on Oct 28th, 2009, 3:52pm Mayank wrote on Oct 26th, 2009, 9:57pm:
If you go one level deeper - Lets take the case of a CMOS inverter: It is a diode connected PMOS transistor connected to a diode connected NMOS transistor. No oscillation, no inversion. As for the two voltage sources connected to each other? Does not exist in the real world, its an academic abstraction. All voltage sources have impedance. If you can give me an ideal voltage source with no impedance we can solve the energy problems of the world by pulling 10E999 amps of current out of it. :D As for the other answers provided - I see the word "assume" being used a bit too much in the answers. As long as the assumptions are clearly stated, that's cool, but make sure the assumptions are applicable and valid to the original question asked. In my experience they generally are not, but that gets conveniently forgotten a little too often. |
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Title: Re: Regulator Question Post by thechopper on Oct 28th, 2009, 7:57pm raja.cedt wrote on Oct 26th, 2009, 9:56pm:
Regardless these are OTAs or OPAMPs both can be modeled by two voltage sources with a finite impedance (high for the OTA, low for the OPAMP and least at low freq). (see drawing) Note: Although the OTA is usually modeled as a controlled current source and therefore it has an output shunt impedance this assumption is still valid. The non-zero output impedance is a valid assuption since we are talking of actual amplifiers (as Jerry suggested before this circuit does not make sense for ideal OPAMPS, and even for ideal OTAS it does not make sense to consider both have different input referred offsets....otherwise they would not be ideal :)) So if V1 is the first amp and V2 the second amp, then V1= 10mv and V2= 20mv. Therefore Vo will be the voltage division of these two voltages. I suggested that if the open loop gain is not greatly affected by the different unbalances, then Z1 and Z2 will be similar and Vo should be close to 15mv. Otherwise Vo wil be set by the corresponding voltage division Best Tosei |
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Title: Re: Regulator Question Post by raja.cedt on Oct 28th, 2009, 9:11pm hi, thanks for Tosei, for clarifying division concept. Thanks every body who has given inputs to this question. Thanks. |
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Title: Re: Regulator Question Post by boe on Oct 29th, 2009, 11:38am loose-electron wrote on Oct 28th, 2009, 3:52pm:
BOE |
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Title: Re: Regulator Question Post by loose-electron on Oct 29th, 2009, 4:41pm Ah! Exactly! As you can see, you have to go that "one level deeper" before you have a meaningful question that can be answered! Also, notice I said "CMOS inverter" and that was intentional, because there were some forms of multi transistor TTL that the answer would have been totally different. |
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Title: Re: Regulator Question Post by Mayank on Oct 29th, 2009, 9:49pm Hi, thanx Jerry....I understood the functioning... @ Boe : Can you explain what do you mean by 3-stage Inverters ?? regards, mayank. |
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Title: Re: Regulator Question Post by loose-electron on Oct 30th, 2009, 8:39am The three stage inverter is generally 3 inverters in series, in ->inv1->inv2->inv3->out as you go from stage to stage, the transistor sizes get larger so the output can drive larger loads. |
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Title: Re: Regulator Question Post by Mayank on Oct 30th, 2009, 3:19pm Hi jerry, Ohh, it's that 8-) ...I usually call it clock/data buffer-chain....Increases drive....I got it...I thought it was some fundoo Inverter design with 3 MOSes like some current-starved kinda thing... ;) thanx, Mayank. |
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