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Design >> Analog Design >> maximum power dissipation per active area
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Message started by XY-oriented on Oct 28^th, 2009, 2:53am

Title: maximum power dissipation per active area
Post by XY-oriented on Oct 28^th, 2009, 2:53am

hello every one ;-)
does anyone has an estimate or guideline about the maximum power dissipation per active area that should not be exceeded for save operation ?

the foundry provides maximum Ids*Vds/μm width but specifically states that it should not be interpreted as the maximum power dissipation allowed (because of packaging and other stuff).

how do you guys usually size your power devices ?

thanks a lot.

Title: Re: maximum power dissipation per active area
Post by loose-electron on Oct 28^th, 2009, 4:09pm

That generally gets broken into several separate things:

1. Current density for a defined element - Usually a max current is defined for a given geometry of a given circuit element. Lets say a 1u wide resistor is limited to 100uA, so if you go to a 2u wide resistor, you can put 20uA in it. (numbers are not real)

2. Electromigration current and voltage rules. These are unique to a foundry process. See the PDK and associated documentation.

3. Thermal elevation: Wattage dissipated in the chip (usually done in degrees C per watt as part of the package rating) will lead to a thermal limit violation. If it runs in a 30C environment, and the package thermal rating says you are elevating the chip 90 degrees means the chip is at 120C inside the package. If the foundry says the silicon is only good to 100C you have problems.