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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> questions about amplifier DC biasing https://designers-guide.org/forum/YaBB.pl?num=1256866959 Message started by LeonQQ on Oct 29th, 2009, 6:42pm |
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Title: questions about amplifier DC biasing Post by LeonQQ on Oct 29th, 2009, 6:42pm Hello folks, I wonder in real chip testing, how do people set up the DC biasing to the OTA input nodes Vin+ and Vin- as shown in the figure below. The pseudoresistors Mb1 -Mb4 provide very high resistance (~ 10G ohm) thus making the nodes Vin+ and Vin- almost floating in reality. Thank you all. Leon [img][/img] |
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Title: Re: questions about amplifier DC biasing Post by Mayank on Oct 29th, 2009, 10:28pm Hi Leon, The i/p nodes of an OTA are generally set by the o/p CM level, in most of the cases i/p CM being equal to o/p CM...The -ve terminal is biased by the o/p node through Mb1 & Mb2 ....On the +ve node, the OTA i/p is biased through the branch Mb3-Mb4 from vdd/2 High Resistances (~ 10G as you said) ensure that your AC signal doesnt cross them. On the other hand, for DC current, since there is no DC current flow allowed at i/p node because of i/p caps...The i/p node settles to the voltage on the other end of the High-Resistance, since the drop across the resistor is ZERO..... regards, Mayank. |
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Title: Re: questions about amplifier DC biasing Post by LeonQQ on Oct 30th, 2009, 9:21am Thank you Mayank. In the lab testing, when I change the DC at Vref node, the OTA output wave changed drastically. It looked to me that the DC at Vin+ node was disturbed by the DC change at Vref node. But How come the DC change coupled through the cap? Maybe I changed the DC too quickly, then it changed the charge at Vin+ node through charge injection. But the problem is that the DC at Vin+ and Vin- seemed not being able to settle to Vdd/2 correctly. |
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Title: Re: questions about amplifier DC biasing Post by Mayank on Oct 30th, 2009, 3:00pm Hi Leon, Answer to your question : Yes, if you change your DC level too quickly, it will couple and you will see a charge-sharing/feedthrough...It's categorized as a Fast transient effect...As for your query that Vin+ and Vin- are not pinning at Vdd/2, -----> 1. First of all, are you using an OTA or an opamp ? i hope you didnt mistakenly write OTA instead of opamp.... 2. In an opamp, o/p CM voltage is always of a concern in analog ckts, since it biases the next stage...So you have a CMFB Loop to control the O/p CM level....There you can use this o/p CM Level to bias the input at a fixed CM level, common for both i/p and o/p(set by CMFB Loop) On the Other Hand, In you OTA, If you have a well defined CM level(a single-ended implementation or a CMFB control in a differential one), then you can use o/p to bias i/p through a high-resistance path Mb1-2, OTHERWISE both Vin- and o/p will settle at the o/p CM level generated(which you cant be certain that it's vdd/2) regards, Mayank. |
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Title: Re: questions about amplifier DC biasing Post by LeonQQ on Oct 30th, 2009, 3:31pm Thank you Mayank for your help. I use a single-ended OTA (high impedance output node). |
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Title: Re: questions about amplifier DC biasing Post by ic_engr on Nov 2nd, 2009, 11:28am I guess the goal is to have a very low High Pass corner using this large resistor. Note that the resistor is signal dependent. What happens if the signal at the o/p of the opamp is close to rail-rail, the MOS transistors channel resistance woudl surely reduce and the output signal may dsitort. How would this be handled ? Any ideas or suggestions. ic_engr |
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Title: Re: questions about amplifier DC biasing Post by LeonQQ on Nov 2nd, 2009, 1:18pm Hello Ic-engr, you are right, when the output swing goes high, the pseudo-resistor value goes down, this is one of the disadvantages of this circuit |
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Title: Re: questions about amplifier DC biasing Post by Mayank on Nov 2nd, 2009, 9:13pm Hello Leon & ic-engr, The effect you are pointing out is inevitable if you use these kind of psuedo-resistors...Why dont you guys use poly-Si resistors instead of diode-connected devices...Because of these effects, esp. in filters where linerarity is a concern, we use poly resistors. Also, you can try triode-biased devices...Maybe that will help.. There are many ways to implement a high Resistor value....Most feasible being Swithed-Cap implementation....What say ? --Mayank. |
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Title: Re: questions about amplifier DC biasing Post by LeonQQ on Nov 2nd, 2009, 10:55pm Hello Mayank, it depends on applications, I used this amplifier for bio-medical purpose, I need a high-pass pole around less than 1 Hz to reject DC offset introduced by electrode-tissue interface. The triod-biased MOS need a well controlled gate bias which can be costly to generate on chip. Switch-cap need clocks and also not suitable for this extremely low-noise application. Besides, I found it was actually the on-board buffer and oscilloscope probe causing the measurement problem. DC bias is ok. But since I am trying to probe the high-impedance output node, I buffered it through an discrete buffer, but the buffer itself introduced a lot of noise and distortion, since my input is in the mV range. Is there a good way to probe a high-impedance node without buffer it on board? Thank you |
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Title: Re: questions about amplifier DC biasing Post by Mayank on Nov 3rd, 2009, 12:07am Hi Leon, You want to probe a high-impedance node...& want DC signals to be filtered...In short, you need a high-pass with wery low cut-off as you said earlier....Try a L-C high pass filter...You can use active-inductors if you want.....+ it can be on-chip...what say ?? |
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Title: Re: questions about amplifier DC biasing Post by vivkr on Nov 3rd, 2009, 2:38am LeonQQ wrote on Nov 2nd, 2009, 10:55pm:
Hi Leon, I would say No! there is no good way to probe a high-impedance node without a buffer. As a matter of fact, the chances of ruining performance are very high if you take out a high-Z node off-chip for direct probing. So the buffer solution is fine as long as you are not trying to see the input DC level with a high accuracy. I would try only to see the DC level there, and be aware that the buffer introduces some error too. It would be difficult to verify the < 1 Hz cutoff at input by direct probing. However, you should see the characteristic when you probe your amplifier output. So I see no real reason for direct probing of the input. As for the rest, what you are doing is quite a standard practice. Regards, Vivek |
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Title: Re: questions about amplifier DC biasing Post by LeonQQ on Nov 3rd, 2009, 4:36pm Thank you Vivkr, I am searching for some low-noise low-voltage discrete commercial opamp as my buffer. |
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