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Design Languages >> Verilog-AMS >> What does -: mean?
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Message started by Mike_k on Oct 30^th, 2009, 5:17pm

Title: What does -: mean?
Post by Mike_k on Oct 30^th, 2009, 5:17pm

For example: bus_name[32-:8]

Title: Re: What does -: mean?
Post by Geoffrey_Coram on Nov 2^nd, 2009, 5:45am

I thought it was a typo, but I do see that syntax in 1800-2005.

I think it was intended to allow you to grab a fixed-size slice of an array:

Quote:

The size of the part-select or slice must be constant, but the position can be variable. The syntax of Verilog is used.
int i = bitvec[j +: k]; // k must be constant.

So, in your case, I think [32-:8] is the slice starting at 32 and going down to get 8 bits, and thus would be the same as [32:25]. However, you could also have bus_name[x-:8] and sometimes x=32 and other times x=24, etc.