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Design Languages >> Verilog-AMS >> analog signals in busses
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Message started by Riad KACED on Nov 2^nd, 2009, 1:10pm

Title: analog signals in busses
Post by Riad KACED on Nov 2^nd, 2009, 1:10pm

Dear All,

Can someone shed some light on the following passage from the 'THE DESIGNER’S GUIDE TO VERILOG-AMS', page 86:

Quote:

For reasons that are more difficult to explain, from within analog processes any access to the analog signals in busses also must be statically associated, and so can only be included in loops that are restricted by having a genvar index.

I am pretty much sure Ken has left the details for good reasons, I'm a bit curious to know those details though ...

Thank you very much in advance.
Regards,
Riad.

Title: Re: analog signals in busses
Post by Geoffrey_Coram on Nov 6^th, 2009, 12:00pm

Don't forget the next sentence, "This is true regardless of whether the signals are being observed or driven."

I(out) <+ V(bus([i]);

I(bus[i]) <+ V(in);

In either case, there needs to be a matrix entry in the circuit (Jacobian) matrix, reflecting the fact that a change in the "sensed" value (RHS) causes a change in the driven value (LHS). In a sparse matrix, one only allocates matrix entries that are needed, and the genvar construction allows the compiler/simulator to know which matrix entries are needed.

On the other hand, it seems the bus is of a fixed width, so a pessimistic compiler could allocate all the matrix entries (and, in many modules, one can probably access any signal in the bus, so it's not too pessimistic).

I also expect one could "observe" a bus value using $strobe without a genvar index, no matrix entry is needed.

Title: Re: analog signals in busses
Post by Riad KACED on Nov 9^th, 2009, 11:43am

Hi Geoffrey,

Thank you very much for your explanation, that's clearer in my mind.
I haven't tried the $strobe and i think I'd stick at the genvars anyway.

Cheers,
Riad.