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Design >> RF Design >> Matching Networks
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Message started by aaron_do on Nov 3^rd, 2009, 4:48pm

Title: Matching Networks
Post by aaron_do on Nov 3^rd, 2009, 4:48pm

Hi all,

For LNA input matching networks, it seems that the variation can be very high from simulation to measurement. For example, you need to match to some on-chip resistance. The most common ways i know to define the resistance are...

1. Common-gate architecture
2. resistive drain-gate feedback
3. An on-chip resistor
4. inductive degeneration

For 1. and 2., I can see that they can be matched to an off-chip resistor and perhaps can be quite accurate. However, for 3, the on-chip resistor can vary by up to 50% and in 4., the resistance depends on the biasing conditions, Ls and the process. I'm not exactly sure but I guess it can also vary by a similar amount. Apart from that, L and C can also vary on-chip. Does anybody have any comments on how to reduce the variation of such matching networks? Resistor trimming is not an option...

For a lot of commercial designs, i've seen that they don't bother to match to 50ohm, but simply quote the input impedance. Is this standard practice?

thanks,
Aaron

Title: Re: Matching Networks
Post by RFICDUDE on Nov 5^th, 2009, 4:10pm

It is a good idea to scope out the problem first.
Generally a VSWR of 2:1 or a return loss of -10 dB is ok worse case (ok many LNA circuit would like a RL more like -15dB).
A VSWR of 2:1 allows a pretty wide impedance variation window (25 ohms on the low side and 100 ohms on the high side for a 50 ohm system).

Integrated resistors maybe have +/- 25% variation (I assume this is the 50% you mention) at worst. Thin film metal resitors maybe much better than this. So you have a fighting chance with on-chip resistive loads; although, you can throw low NF out the window.

#2 is somewhat attractive because the loop gain helps to reduce the variation due to gm and R process variation. There have been several papers on "inductorless" LNAs using shunt feedback to both set the wideband input impedance and provided reasonably low NF (2.5dB).

Now you should also consider the reactance variation too. The input capacitance may vary as much as +/- 25% independently of the resistance variation. This can be particularly an issue for reactive matches since the match is much more sensitive to reactive variation. Here I can't offer much help because you need some "patent" worthy solutions to solve the problem.

Title: Re: Matching Networks
Post by aaron_do on Nov 6^th, 2009, 3:44am

Thanks for the reply.

the reason I wanted to concentrate on the resistive part is because my understanding was that on chip capacitors can be accurate up to 10% and inductors even better. If we make such capacitors large compared to the input capacitance of the devices, the overall reactance variation should be small...

So far I have been using poly resistors, and I think their variation is pretty bad. Either that or you can match to the series parasitic resistance of an inductor. Not sure how variable that is.

I'm still wondering what the industrial standard method is...

cheers,
Aaron

Title: Re: Matching Networks
Post by Mayank on Nov 6^th, 2009, 5:50am

Hello aaron,
I dont have much experience in the area...But can't we use active resistors (linear-biased MOSFETs) ?? ....That will give you a control over their resistance + that resistance will track with process variations....

If linearity is an issue, there are structures which provide non-linearity cancellation to a good extent....Active Devices can introduce extra noise though, which i agree is a chief concern in an LNA....You would hv a better idea whether this trade-off works well or not ?

regards,
Mayank.

Title: Re: Matching Networks
Post by RFICDUDE on Nov 6^th, 2009, 7:25am

I would be very interested to know if there is an industry standard way of doing it. But the problem depends on topology and the specifications the circuit needs to meet (RL, NF, gain, IP3, ...), so I doubt there is a universal solution.

Title: Re: Matching Networks
Post by loose-electron on Nov 6^th, 2009, 10:21am

most matching networks are kept outside the chip for a very simple reason - you need to match to the PCB, I/O, package, and the LNA input.

Worst case its 2 C's and one L, and you are done. By keeping it outside you can use high quality devices and have complete freedom tweaking the device after its fabricated.

Bottom Line: Matching networks are generally kept outside the chip for good reasons.

- my 2 cents worth
- Jerry