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Design Languages >> Verilog-AMS >> Trouble with veriloga in Spectre 6.x simulator
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Message started by McSim on Nov 10^th, 2009, 7:44am

Title: Trouble with veriloga in Spectre 6.x simulator
Post by McSim on Nov 10^th, 2009, 7:44am

Hi all!

I have a problem with Verilog-A modeling in Spectre 6.x.

I use BSIM3 model implemented in Verilog-A by Geoffrey Coram (the file was available at Silvaco and then - at Simucad site some time ago). See attached file. I have successfully used it with Spectre 5.1.41.

My "standard" task is to simulate MOSFET DC characteristics. Transistor is taken from PDK. In model file there is a subckt which uses the instance described as Verilog-A module (using "ahdl_include"). All SPICE parameters are described as instance parameters (instance inside subcircuit):

inline subckt nmos_tn (d g s b)
parameters w=1E-7 l=1E-7 PAR=1 as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0
...
nmos_tn (d g s b) bsim3mos W=w L=l AD=ad AS=as PD=pd PS=ps ...
+ TYPE=1
...
+ U0=0.035597185
...
ends nmos_tn

, where "bsim3mos" is verilog-A module.

But when I try to simulate this with Spectre 6.0 or even with Spectre 6.2 some Verilog-A module parameters are not recognized as instance parameters by simulator (and some parameters, e.g. W, L, TYPE and TOX are still recognized, but U0 isn't). Warning message is generated:

"U0 is not a valid parameter for an instance bsim3mos. Ignored"

And then characteristics with default values (defined in Verilog-A module) of parameters are simulated.

Could you help me to solve this problem or just give an advice how should I search the possible reasons?

P.S. By the way, does anybody know why the files with Verilog-A MOSFET models are not available now?

Title: Re: Trouble with veriloga in Spectre 6.x simulator
Post by McSim on Nov 11^th, 2009, 3:39am

I've solved my problem... The reason was just one string in simulator options:

simulator lang=spectre insensitive=yes

The correct variant is following:

simulator lang=spectre

There was intrinsic conflict with parameters in upper register (which were instance parameters) and lower register (local variables).

Title: Re: Trouble with veriloga in Spectre 6.x simulator
Post by cryogenic on May 3^rd, 2011, 11:32pm

Hi,

I am working on low temperature MOSFET modeling, for which verilog-a implementation of BSIM3 model is required. I could not locate it at the SILVACO site or from any other source. If someone who has the code could share it, that would have been really helpful.

Title: Re: Trouble with veriloga in Spectre 6.x simulator
Post by Geoffrey_Coram on May 4^th, 2011, 9:56am

McSim seems to have posted it -- "See attached file." in the first post of this thread.

Note: I didn't actually write this file, I just offered some suggestions for improvements. Silvaco then credited me, but not their employee who did all the real work.

Title: Re: Trouble with veriloga in Spectre 6.x simulator
Post by McSim on May 5^th, 2011, 12:09am

cryogenic, I've answered via e-mail.

I've modified the "original" file from Silvaco a little bit to make it compatible with Spectre simulator. This modified file is attached in the first post.

Title: Re: Trouble with veriloga in Spectre 6.x simulator
Post by cryogenic on May 8^th, 2011, 11:17pm

Thanks Dr. Coram and McSim for you replies. I could get the file from the first post in the thread.

McSim, I got your email as well. Thanks a lot for the information you have passed on.