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Design >> Analog Design >> Mismatch
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Message started by raja.cedt on Nov 12^th, 2009, 9:19pm

Title: Mismatch
Post by raja.cedt on Nov 12^th, 2009, 9:19pm

hi,
i have an doubt in the pelgrom paper (exact title is Matching properties of mos transistors, October89,dec jssc ). In the fig 8 he is plotting mismatch in current vs gate voltage, so i agree that at low Vgs mismatch in current will decrease with Vgs but in fig it seems like it is continuously decreasing, but after some voltage i feel device size would be very less and mismatch due to Vt may be less but mismatch due to W/L will increase. Finally what i feel is curve should go up after some Vgs....so please correct if any thing wrong in my argument.
if any one don't have this paper, please send a mail to me.

thanks,
rajasekhar.

Title: Re: Mismatch
Post by Mooraka on Nov 13^th, 2009, 8:18pm

I looked at the plot. I see Ids mismatch decrease with increase in Vgs for a fixed W/L. But in your question you are saying "but after some voltage i feel device size would be very less and...". Can you be more clear on the question?

Ram

Title: Re: Mismatch
Post by raja.cedt on Nov 16^th, 2009, 6:22am

hi,
thanks for your reply. What i feel is that in plot the mismatch at constant current, so by increasing voltage we need to decrease mos size..this will increase mismatch due to size.

Thanks,
Rajasekhar.

Title: Re: Mismatch
Post by Mooraka on Nov 16^th, 2009, 9:12am

The plot is not at constant current. The label in the graph shows that it is for fixed W/L=20um/20um, Vdd=5V, Vsb=0V, Vto=0.85V.

ram

Title: Re: Mismatch
Post by loose-electron on Nov 17^th, 2009, 2:12pm

December 1989 paper? The technology has changed so much is this even relevant anymore?

A lot of matching properties are tied to specifics of the process.

As a general rule, bigger devices means better matching, but beyond that it is not wise to draw generalities.

-Jerry

Title: Re: Mismatch
Post by raja.cedt on Nov 17^th, 2009, 8:53pm

hi Jerry,
you are correct man, but i came to industry very recently, here after running Monte i am not able to understand any result, so i am trying to learn some mismatch analysis. can you suggest any reference which will some estimation for present day process?

Thanks,
Rajasekhar.

Title: Re: Mismatch
Post by ywguo on Nov 17^th, 2009, 9:50pm

Hi Jerry,

I looked that paper again. Figure 8 is Ids mismatch vs Vgs for a fixed W/L transistor. The mismatch current Ids decreases when Vgs increases. The mismatch of the threshold voltage δ(Vth) is one important factor that affects δ(Ids). However, δ(Vth) becomes a smaller portion when Vgs increases. So I think this is a general rule now. Do you agree on my opinion?

Best Regards,
Yawei

Title: Re: Mismatch
Post by Mayank on Nov 18^th, 2009, 4:04am

Hello,
I agree with ywguo as far as you consider only vds mismatch and ignore all other device mismatches....As vgs increases, delta Vt becomes a smaller proportion and hence mismatch improves...
...Considering device size mismatches, larger the device, larger the lengths, lesser the mismatches...
....These could be taken as general rules...

@ raja : As for mismatch, i monte-carlo the design over 200-300 runs & take 3-sigma or 5-sigma variation...

--mayank

Title: Re: Mismatch
Post by rajdeep on Nov 18^th, 2009, 4:22am

Quote:

larger the device, larger the lengths, lesser the mismatches...

What I knew, larger the area, lesser is the mismatch. So even keeping L same, if I increase W, mismatch should reduce. Does it have more impact if we increase L, rather than W?

Just wonder, if for same area increase is it more prudent to increase both W and L, rather than increasing only one of them? Well, I think that anyway has to be done, as W/L ratio will be governed by something else. But just wondering if no such restriction is there on the ratio!! :-/

Rajdeep

Title: Re: Mismatch
Post by Mayank on Nov 18^th, 2009, 6:13am

@ rajdeep :

1 --> Larger the device, lesser the mismatch....
2 --> Larger the length, lesser the channel-length modulation effect, means larger the ro, so lesser the mismatch in ro coz of mismatch in farication of L....
3 --> W/L ratio is governed by your ckt design, while mismatch dictates your Area, so since the ratio is fixed, you generally have to increase L. You can also change W/L ratio to improve mismatch and save on area but then you relax on some spec,say vgs/vds/ro of that particular MOS.

--> Didnt understand the second para of your post
Quote:

Just wonder, if for same area increase is it more prudent to increase both W and L, rather than increasing only one of them? Well, I think that anyway has to be done, as W/L ratio will be governed by something else. But just wondering if no such restriction is there on the ratio!! :-/

For same area, how can you increase both W & L ? :D One has to decrease to increase the other....
For answer on W/L restrictions, see point 3.

--mayank

Title: Re: Mismatch
Post by rajdeep on Nov 18^th, 2009, 7:11am

Hmm!! you missed the word 'increase'. :P I said for same area INCREASE. Now we can increase both W and L as area A = W * L, or either W or L. Since in almost all cases, W/L will be decided by something else, I understand both W and L have to be increased. My question was given an option which one should be increased to minimize mismatch? W or L?

I guess the ans is L as you have mentioned the channel length modulation effect. Was just curious to know abt it.

cheers!
Rajdeep

Title: Re: Mismatch
Post by thechopper on Nov 18^th, 2009, 6:55pm

rajdeep wrote on Nov 18^th, 2009, 7:11am:

There is an important point you are missing here. The criteria for reducing mismatch depends on whether you are considering (1) a current mirror or a (2) diff pair

Just assuming threshold mismatches we have...

Case (1):

ΔI = I1-I2 ≈ gm ΔVTH (neglecting ΔVTH^2 term since it is supposed to be small)

Therefore current mismatch is proportional to gm.....proportional to W!!!. Definitely L is the one to be increased (and then increase W accordingly to keep the same gm as originally)

Case (2):
ΔVTH is directly "at the input" so here in principle is valid to increase either W or L (area at the end of the day). However, the diff pair load mismatches will create a ΔI that will be "reflected" to the input through the diff pair gm ---> we want large gm!!! -->
Input voltage offset is inversely proportional to gm

So in this case it is convenient to increase W (thus increase both area and gm)

Hope this helps
Tosei

Title: Re: Mismatch
Post by Mayank on Nov 18^th, 2009, 9:11pm

Thanx Tosei,
Your answer explains it all....
mayank.

Title: Re: Mismatch
Post by rajdeep on Nov 19^th, 2009, 1:15am

Hi Tosei!

Spot on! Thanks a lot!

But isnt it, that in the case of a diff amp (i guess in every case), the gm of the input pair will be determined by the other specs (gain, ugb,noise)? That will fix the W/L. So any area increase to improve matching, can be done by increasing both W and L (since W/L is already fixed), in all practical situations of designing a diff amp. But I appreciate your point of view, as I myself asked, given a choice (as if W/L is not fixed) what is preferred . And I agree with you that in case of diff amp one would like to increase W, rather than L for higher gm, quite opposite to what one would do in case of current mirror!!

Thanks again!
Rajdeep

Title: Re: Mismatch
Post by raja.cedt on Nov 20^th, 2009, 7:33am

hi rajdeep,
always mismatch and noise in current mirror and diff amp are quite opposite, see in current mirror if you want less mismatch in current, keep your overdrive less,where as in diff amp you need less overdrive.
if you calculate properly mismatch in % of current it is independent of width

Thanks,
Rajasekhar.

Title: Re: Mismatch
Post by RobG on Dec 14^th, 2009, 7:49pm

HdrChopper wrote on Nov 18^th, 2009, 6:55pm:

Oh I miss the days when i seemed to be the only one who seemed to know this stuff ;) Great explanation, but one minor issue, which I expect was just a typo. Mismatch isn't proportional to W in a current mirror. When considering the mismatch in a current mirror, it is independent of width: as width goes up, gm goes up, but also ΔVth goes down so they cancel each other (at least in ideal strong inversion). But I agree, increase L (or current) and then adjust W to get the same Vgs-Vth.

In an opamp current mirror mismatch also gets input referred via the gm of the diff pair. In other words, you should always have the gm of the diff pair much larger than the gm of your current mirror. You can see it in the equation
Vos^2 = ΔVth_diff²+(gm_mir/gm_diffΔVth_mir)²

Another way to think about it is to maximize the overdrive (i.e. Vgs-Vth) of a current mirror and minimize overdrive for a diff pair. In the end you need to fit everything between the rails so that is what you need to do physically. Chew up as much headroom as possible with your mirror, not your diff pair.

RE the original question, the reason the mismatch got better with more overdrive is because the ΔVt becomes negligible compared to the overdrive voltage (Vgs-Vth). Once this happens the mismatch is determined by β mismatch. You can see it in the equation:
I+ΔI = (β+Δβ)(Vgs-Vth+ΔVt)²
You can solve this for ΔI/I.
But as Tosie noted, this is the case of a current mirror.

Sigh, I'm always late to these things.
Rob