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Design >> Analog Design >> Vds- Matched V-2-I converter design
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Message started by Mayank on Nov 18^th, 2009, 7:06am

Title: Vds- Matched V-2-I converter design
Post by Mayank on Nov 18^th, 2009, 7:06am

Hello Guys,
I am trying to design a vds-matched V-2-I converter.....Schematic is shown in the figure attached....

My belief is that the opamp will ensure that nodes Vx & Vy sit at same voltage levels, so that the vds & vgs for both branches is same, hence ensuring properly matched current...Can someone give more insight into the ckt operation ??
There are two loops that are formed, one is +ve feedback [T1-Vx-Opamp] and the other -ve feedback [T0-Vy-Opamp]...How do i ensure stability of this ckt ??

Title: Re: Vds- Matched V-2-I converter design
Post by thechopper on Nov 18^th, 2009, 6:19pm

Hi Mayank,

Generally speaking, the +ve feedback loop has to have less gain than the -ve one. In that way a stable operating point can be achieved for the ckt.
Both loops share a common branch: the opamp´s output. so you can "break" the loop right there and analyze it as if it was a single loop (this is one of the scenarios that a multiloop ckt can be analyzed as a single loop one).

Hope this helps
Tosei

Title: Re: Vds- Matched V-2-I converter design
Post by Mayank on Nov 18^th, 2009, 8:44pm

Thanx Tosei,

The input at Vin will change the current in 1st branch, changing the voltage at Vx...Opamp will try to settle Vy to the same voltage, & current in second branch will be decided by Vy/Rload & NOT VIN.....This action doesnt reflect a current source, instead a voltage source
Am i mistaken somewhere ?
In this case, Rload represents the incremental resistance of a CCO....I want a costant current into Rload....
Are there some modifications i need to make ??

--mayank.

Title: Re: Vds- Matched V-2-I converter design
Post by Mayank on Nov 19^th, 2009, 3:01am

Hello all,
I am simulating the above attached ckt....But something unexpected is happening....
Opamp Open Loop response is stable with a PM of around 60 deg. I am breaking the loop at the common point.
Accroding to my calculations, -ve FB Loop should be stronger than +ve FB Loop...I am confused, esp by looking at the phase response...Is this way of measurement correct ??

Can't attach two files in one post :--- 1st image --> opamp Open Loop Response

Title: Re: Vds- Matched V-2-I converter design
Post by Mayank on Nov 19^th, 2009, 3:17am

Continued.....Refer to post above.
2nd. image :---> Current Mirror Response on breaking the loops at their common point

Could somebody guide me past this ?

thanx,
mayank

Title: Re: Vds- Matched V-2-I converter design
Post by Dipankar on Nov 19^th, 2009, 7:54am

Better use stability ("stb") analysis of spectre. Insert a vdc = 0 volt at the branch connecting OPMAP output to the PMOS gate. (bcz this is the branch which is common to both the loops).

Title: Re: Vds- Matched V-2-I converter design
Post by Mayank on Nov 19^th, 2009, 10:18am

Hello,

@ dipankar : tried and tested all three methods for stability checks...

for everyone :
1. Middle-Brook Method
2. LC Filter for finding AC Loop Gain while maintaining DC Bias
3. Stb analysis of specte using iprobe

All three of them give same results....[Just remember in method 2 to put very high values of L ~ 1GH and C~ 1F]

Can i find analysis of a ckt of this kind anywhere ?? Am not able to stabilize it :(

--mayank

Title: Re: Vds- Matched V-2-I converter design
Post by thechopper on Nov 19^th, 2009, 5:18pm

[quote author=Mayank_Singh link=1258556820/0#2 date=1258605890]Thanx Tosei,

The input at Vin will change the current in 1st branch, changing the voltage at Vx...Opamp will try to settle Vy to the same voltage, & current in second branch will be decided by Vy/Rload & NOT VIN.....This action doesnt reflect a current source, instead a voltage source
Am i mistaken somewhere ?
[quote]

Hi Mayank,

In my opinion you do have a voltage controlled current source, since Vx is controlled by Vin, and Iout is a function of Vy=Vx.
The observation is that the output current is not a linear function of the input voltage, but still it is controlled by it.
What it looks to me is that if you want a more linear control on the current you then need to size the controlled NMOS such that it operates in triode region....

Best Tosei

Title: Re: Vds- Matched V-2-I converter design
Post by thechopper on Nov 19^th, 2009, 5:23pm

Mayank wrote on Nov 19^th, 2009, 10:18am:

From you bode plots it looks the current sources add an additional 35 phase at UGF, achieving ~ 25 deg of PM.
What if you just try to make your opamp more wideband?....That way you PM will start improving and you will get the overall circuit more stable.

Best
Tosei

Title: Re: Vds- Matched V-2-I converter design
Post by Mayank on Nov 19^th, 2009, 10:56pm

Thanx Tosei,
Found the problem --> The ckt works fine if i replace the i/p Mos + src-Degeneration res with one single resistance whose value is in coordination with my math. High ro is causing a problem i suppose....
But if i try to increase the BW of the opamp, -->
1. Error Amplifier is supposed to be of as low a BW as possible....Here, i am using the opamp as an error amplifier b/w vx & vy nodes....Increased BW would allow more noise to be pumped in...
2. Increased Power Consumption...

Using input MOS in triode region is a nice suggestion, would try that for sure....But i still didnt understand how increasing opamp UGB would improve PM ?

--mayank

Title: Re: Vds- Matched V-2-I converter design
Post by thechopper on Nov 28^th, 2009, 9:48am

Hi MAyank,

My bad. I meant making the opamp more narrowband, so you get a heavier pole splitting and the phase contribution from the current mirror does not degrade that much your PM.

Best
Tosei

Title: Re: Vds- Matched V-2-I converter design
Post by Mayank on Nov 28^th, 2009, 10:45am

Hello Tosei,
Thanx for your answer....but i thought we need a narrow band opamp for some other reasons which i stated in my post above....

Could you pls emphasize more on what you meant by
Quote:

making the opamp more narrowband, so you get a heavier pole splitting and the phase contribution from the current mirror does not degrade that much your PM.

I didnt understand this statement quite well....

thanx,
mayank