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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Sigma-Delta modulator distortion and timing issue https://designers-guide.org/forum/YaBB.pl?num=1259650632 Message started by pilo on Nov 30th, 2009, 10:57pm |
Title: Sigma-Delta modulator distortion and timing issue Post by pilo on Nov 30th, 2009, 10:57pm hello, all: I'm simulating a sigma-delta modulator recently, and I take the timing scheme of the attachment. The problem is that I always run into high 3rd harmonic distortion, what can probably cause that? (Ideal opamps are used, so the nonlinearity of opamp can be omitted) An other question is that why an advanced clock phase is used to drive the DAC feedback logic? I thought that will cause signal dependent charge injection, isn't it? I will appreciate you reply, thanks. |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by sheldon on Dec 1st, 2009, 4:01am Pilo, Could you provide any other details, for example, the how are the switches modeled? What is the switch on-resistance? Best Regards, Sheldon |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by pilo on Dec 1st, 2009, 5:11am hi, sheldon, For sampling switch of stage 1, a CMOS transition gate is used and the simulated on resistance is around 200 ohm. Other switches is either realized by a single NMOS or a PMOS transistor, both very large to lower the on resistance, in stage 1. In other stages, the switches are scale down. Does the charge injected by these switches cause the harmonic distortion? I thought the charge injection is signal independent and canceled by the fully differential configuration, am I right? Or there is something to do with the timing scheme? Regards, pilo |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by sheldon on Dec 4th, 2009, 6:22pm Pilo, Since the op-amps are ideal, they probably are not causing the problem: 1) Are the capacitors linear capacitors or are they device capacitors? If the device capacitors are model as non-linear devices, then the you might try replacing them with linear capacitors. If the distortion improves, then the issue is the device capacitor non-linearity. 2) Switch test 1: You might try replacing the capacitors with the switch from bmslib. sw_no. This will allow you to see if the issues is the switches. If the distortion improves then the issue maybe that the switch on- resistance needs to be more linear across the voltage level. 3) Switch test 2: Use the bmslib switches and lower the on-resistance, if the distortion improves, then there maybe a settling issue, the switch R X Capacitor RC time constant is too long for the time allowed to settle. Or incomplete settling is the source of the distortion. 4) You might also want to verify your assumption that the op-amps are ideal. If the op-amp models are not ideal then there are other issues that need to be explored. 5) BTW, you have not provided much detail so my assumption is that you are designing an audio SD expecting ~90-96 dB of SINAD are seeing ~70-80dB due to large distortion tones. That is basically you are close to your expected results with more distortion than expected. In addition, the other assumption is that structure is fully balanced, timing is correct, and the op-amps have high CMRR so that the effect of charge injection, ... can be neglected. This is nice place to use behavioral modeling to help you isolate the issue. Best Regards, Sheldon |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by pilo on Dec 6th, 2009, 8:19pm Sheldon, Thanks for you reply! In fact the modulator is used in an MEMS readout circuit that require a 18bit resolution and the signal bandwidth is 1K Hz. I don't quite understand the nonlinearity effect of on resistance as you mentioned. To my understanding, the on resistance will only affect the settling behavior of the sampling circuit, is it OK that I ensure that the on resistance be low enough during all voltages instead of concerning its linearity? Another question, to suppress the flicker noise, a CDS configuration is used in the first integrator. However, according to simulation, the rms noise integrated from 0.1hz to 1K hz is even larger than circuit without a CDS during clock phase T1, how could that happen? best regards, pilo |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by Berti on Dec 7th, 2009, 3:24am I would recommend you to first do some additional reading (such as Design of Multi-Bit Delta-Sigma A/D Converters from Geerts, Steyaert and Sansen) to get a complete overview of non-idealities in the circuit. From this you should derive the circuit block specifications. Otherwise I might be difficult to achieve 18bits of resolution by just trusting the simulator... Cheers |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by loose-electron on Dec 7th, 2009, 8:49pm Suggest - go back to an all ideal model (perfect everything, switches, amps, ideal timing, etc) as a start point. Get the performance there. Then start introducing the real circuits. Build it stage by stage there and see what happens. Also, if you havent done it already, do you have a purely math model of this? Good luck with it - 18 bits is not easy, but it can be done. |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by pirate on Dec 15th, 2009, 9:29am since your switches are at transistor level, don't underestimate their non linearities. A low on resistance is not enough, if the resistance changes with the signal amplitude it will increase distortion especially if your settling is not a 1st order type (1-e^(-t/TAU)). Have you look at your clock generation circuit waveforms as well ? nice and cleanly spaced ? |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by Berti on Dec 20th, 2009, 1:41pm Pirate is right: The "complete settling" argumentation for the switches holds only for those switches where the input signal is already sampled. This is not true for the input sampling switch. Cheers |
Title: Re: Sigma-Delta modulator distortion and timing issue Post by pilo on Dec 24th, 2009, 6:03pm hi, all Thx for your replies! I confused the input signal and the sampled signal just as Berti said. Now the linearity of the input switch is the key problem, and I found that a boot strapped switch will solve it for instance the configuration mentioned in M. Dessouky and A. Kaiser's paper in 1999. regards, pilo |
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