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Design >> RF Design >> RSSI settling time for a direct-conversion receiver
https://designers-guide.org/forum/YaBB.pl?num=1259811185

Message started by aaron_do on Dec 2^nd, 2009, 7:33pm

Title: RSSI settling time for a direct-conversion receiver
Post by aaron_do on Dec 2^nd, 2009, 7:33pm

Hi all,

I'm trying to figure out how an RSSI can settle properly for a direct-conversion receiver following the IEEE 802.15.4 standard. Assume the RSSI consists of peak detectors which are summed into a LPF and then a 6-bit ADC.

1.) I read in one paper that the chipcon CC2420 RSSI settles in 8 symbols which is 128 us, but I think this includes the time it takes for the PLL to lock. Can anyone confirm this?

2.) Assuming 6-bit accuracy, 0.5LSB=0.78125%. So for the settling time of the RSSI, V=Vmax(1-e^-t/τ). t=4.852τ. Therefore, 128us=4.852τ and τ=26.38us. Does that sound right?

3.) So now I can calculate the minimum corner frequency of the LPF which follow my peak detector as f_3-dB=1/(2πt)=6.033kHz.

4.) This is where it gets confusing. What assumptions can I make about my signal in terms of its bandwidth. My thinking is that the DC-offset cancellation of the front end combined with the low-pass filtering limits the signal to from around 30kHz to 1 MHz (1 MHz is the baseband BW). This signal when squared will have a DC component and a 2nd order component which is spread out from 30 kHz to 2 MHz (right?).

5.) So do we assume the average frequency is about 1 MHz and so for 0.78125% accuracy we need 42 dB rejection? If this is the case, then the 6 kHz LPF at the peak detector output is only just sufficient. However, since the 128us settling includes the PLL settling, it is actually insufficient time for 6-bit accuracy. Does that sound right?

Just as an aside comment, I noticed that many of the IEEE 802.15.4 receivers actually use a low-IF (around 2-MHz). This would avoid the settling time issue of the RSSI...

Any input is welcome,

thanks,
Aaron