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Design Languages >> Verilog-AMS >> odd behavior with trasition filter in Verilog-A / HSPICE
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Message started by bobr on Dec 7^th, 2009, 9:15pm

Title: odd behavior with trasition filter in Verilog-A / HSPICE
Post by bobr on Dec 7^th, 2009, 9:15pm

When I use the transition filter to model a digital signal, it works nicely - as long as I use zero delay. If I put a non-zero number into the optional delay argument, the filter delays the transitions, but then completely ignores the options for rise and fall times. It appears that rise/fall time become shortened to one or two simulator steps, if delay is specified. Here is how I use it:

Code:

V(q) <+ transition( state ? vhi : vlo, 0, trise, tfall);
V(qb) <+ transition( state ? vhi : vlo, delta_t, trise, tfall);

The output of q rises and falls as specified, but the output of qb does not. Is this possibly a bug in HSPICE, or am I missing something?

Thanks, Bob

FYI, I'm using HSPICE version: C-2009.09 64-BIT
and Verilog-A Compiler Version 1.83.100.080509

Title: Re: odd behavior with trasition filter in Verilog-A / HSPICE
Post by patrick on Dec 25^th, 2009, 1:18pm

Hi Bob,

Can you provide the rest of the module and a simple netlist? then we can take a look. HSPICE should control the timestep to maintain the specified rise/fall times properly when a delay is used.

Patrick

Title: Re: odd behavior with trasition filter in Verilog-A / HSPICE
Post by Ari on Jan 19^th, 2010, 5:44am

Bob,

I faced the very same bug with hSpice64 2009.09. Going back to 2009.03 resolved this issue.

I am working with Synopsys AE on creating test-case for this bug, and therefore would like to more information about the netlist in which this bug occured. Please contact me.

Ari