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Design Languages >> Verilog-AMS >> random time delay
https://designers-guide.org/forum/YaBB.pl?num=1260449294

Message started by jdac_18 on Dec 10^th, 2009, 4:48am

Title: random time delay
Post by jdac_18 on Dec 10^th, 2009, 4:48am

I would like to simulate the effects of jitter, but instead of using the standard jitter model, I would like to just randomly delay (positive and negative time) the clock signal. I input the clock signal and then use the latest crossing function and timer to generate a signal. The following is the code I have written:

module timer_test(input_clk, output_clk,rand_tp);
input input_clk;
electrical input_clk;
output output_clk;
electrical output_clk;
output rand_tp;
electrical rand_tp;

parameter integer start_range=-100;
parameter real fs=1/1n, vth=0.5;
integer seed, end_range;
real ran_num,period,d,rand_t,previous,latest;
analog begin
@(initial_step) begin
seed = 50;
end_range=100;
previous=0;
end
ran_num = $rdist_uniform(seed, start_range, end_range);
rand_t=ran_num*1p;
period=1/fs/2;
@(cross(V(input_clk)-vth,+1))begin
previous=latest;
end
@(timer(latest+100p))begin
d=1;
end
@(timer(latest+period+100p))begin
d=0;

end
latest=last_crossing(V(input_clk)-vth, +1);
V(output_clk)<+transition(d, 0, 30p, 30p);
V(rand_tp)<+transition(rand_t,0,0,0);
end
endmodule

The problem is that the random number generated doesn't delay the signal created by the timer function. Is there a way to generate random delay?

Thank you

Title: Re: random time delay
Post by Ken Kundert on Dec 10^th, 2009, 10:56am

Go to http://www.designers-guide.org/VerilogAMS/ and look for "Fixed-frequency oscillators".

-Ken