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Simulators >> Circuit Simulators >> simulator ignores small values in bound_step()
https://designers-guide.org/forum/YaBB.pl?num=1260585749

Message started by bobr on Dec 11^th, 2009, 6:42pm

Title: simulator ignores small values in bound_step()
Post by bobr on Dec 11^th, 2009, 6:42pm

When I use the bound_step() command in Verilog-A/HSPICE, it works as expected for timesteps of 2ps and above. When I try to force a timestep smaller than that, the simulator ignores it, and keeps the timestep at 2ps.

I've tried as many .option settings as I can find, and none seem to effect this limit. Using delmax is not an option, as I need the simulation to take longer steps at other parts in the sim, and only want to force the timestep small at key places.

I extracted the simplest example that displays the problem, and attached the files (an input HSPICE file, and Verilog-A module), in case anyone's interested. The Verilog-A code simply decreases the timestep by 10x from 1ns on down, and the result I see is that the minimum timestep stops decreasing at 2ps, even when bound_test() tries to force 1ps,0.1ps,... The output voltage of the module is equal to the timestep, so that you can observe the value that is being set.

Anyone know why this happens?

Thanks, Bob

Title: Re: simulator ignores small values in bound_step()
Post by pancho_hideboo on Dec 11^th, 2009, 8:36pm

bobr wrote on Dec 11^th, 2009, 6:42pm:

Using delmax is not an option, as I need the simulation to take longer steps at other parts in the sim, and only want to force the timestep small at key places.

Even if you limit max_timestep by using bound_step() in a specific Verilog-A module, simulation timestep of whole circuit is affected by bound_step() in single rate simulator.
So "demax" is same as bound_step().

Do you use multirate simulator ?

Merit of bound_step() is that it can control max_timestep by other parameters.

bobr wrote on Dec 11^th, 2009, 6:42pm:

I extracted the simplest example that displays the problem, and attached the files (an input HSPICE file, and Verilog-A module), in case anyone's interested.

There are no attached files.

Title: Re: simulator ignores small values in bound_step()
Post by bobr on Dec 11^th, 2009, 10:59pm

Hi Pancho,

Yes, I agree with you about the merit of bound_step(), but I think this code shows that it isn't working below 2ps.

Here's my code (sorry the attachment didn't take). It's very short:

HSPICE netlist:
-----------------
*test timesteps
.hdl stepforce.va
.option post
.tran 1p 8n
x1 vtforced stepforce
.end

Verilog-A file: (stepforce.va):
--------------------------------
`include "standard.va"
module stepforce(out);
output out;
voltage out;
real stepsize;
analog begin
@(initial_step) stepsize=10n;
@(timer(1n)) stepsize=1000p;
@(timer(2n)) stepsize=100p;
@(timer(3n)) stepsize=10p;
@(timer(4n)) stepsize=1p;
@(timer(5n)) stepsize=0.1p;
@(timer(6n)) stepsize=0.01p;
@(timer(7n)) stepsize=0.001p;
V(out) <+ stepsize;
$bound_step(stepsize);
end
endmodule

I discussed this with a Synopsys support engineer, and he said that all parts of the circuit should see the same timestep. I guess that means that HSPICE is not a multirate simulator (?).

Even if it was multirate, it seems like the simulator should dis-able that, or at least have an option to disable it, if bound_step() is called. Otherwise, how could they claim to be Verilog-A compliant?

Thanks, Bob

Title: Re: simulator ignores small values in bound_step()
Post by pancho_hideboo on Dec 11^th, 2009, 11:05pm

bobr wrote on Dec 11^th, 2009, 10:59pm:

I discussed this with a Synopsys support engineer, and he said that all parts of the circuit should see the same timestep. I guess that means that HSPICE is not a multirate simulator (?).

Yes, HSPICE is a single rate simulator.

bobr wrote on Dec 11^th, 2009, 10:59pm:

Even if it was multirate, it seems like the simulator should dis-able that,
or at least have an option to disable it, if bound_step() is called.
Otherwise, how could they claim to be Verilog-A compliant?

I can't understand what you mean.
What do you refer as "that", "it" and "they" ?

Later I will check your netlist using many simulators including HSPICE.

Title: Re: simulator ignores small values in bound_step()
Post by bobr on Dec 12^th, 2009, 10:59am

Sorry that was unclear. Let me try that paragraph again:

Quote:

Even if it was multirate, it seems like the simulator should dis-able multirate, or at least have an option to disable multirate, if a bound_step() is called with a timestep smaller than the simulator's current timestep. Otherwise, how could Synopsis claim that HSPICE is Verilog-A compliant?

What I really mean is that, if bound_step() calls for a certain timestep, the simulator should enforce it, regardless of the simulator's internal algorithms.

Thanks for taking a look at it. - Bob

Title: Re: simulator ignores small values in bound_step()
Post by pancho_hideboo on Dec 14^th, 2009, 3:02am

bobr wrote on Dec 11^th, 2009, 6:42pm:

In my environment, $bound_step() works correctly.

HSPICE Netlist(test_bobr.spi)
Quote:

** Generated for: hspiceD
** Generated on: Dec 14 13:52:51 2009
** Design library name: My_RFDE_Test
** Design cell name: test_bobr
** Design view name: schematic
.PROBE TRAN
+ V(vtforced)
+ V(tstep)
.TRAN 1e-12 8e-9 START=0.0

.OP

.TEMP 25
.OPTION
+ ARTIST=2
+ INGOLD=2
+ MEASOUT=1
+ PARHIER=LOCAL
+ PSF=2
.INCLUDE "~/RFDE/test_bobr/bobr.spi"
.END

Spectre Netlist(test_bobr.scs)
Quote:

// Generated for: spectre
// Generated on: Dec 14 14:03:48 2009
// Design library name: My_RFDE_Test
// Design cell name: test_bobr
// Design view name: schematic
simulator lang=spectre
global 0
include "~/RFDE/test_bobr/bobr.spi"

// Library name: My_RFDE_Test
// Cell name: test_bobr
// View name: schematic
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=25.0 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=8n errpreset=moderate write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
designParamVals info what=parameters where=rawfile
save vtforced tstep
saveOptions options save=allpub saveahdlvars=all

Title: Re: simulator ignores small values in bound_step()
Post by pancho_hideboo on Dec 14^th, 2009, 3:11am

bobr.spi
Quote:

*test timesteps
.hdl "stepforce.va"
x1 vtforced tstep stepforce

stepforce.va
Quote:

`include "discipline.h"
`include "constants.h"

module stepforce(vtforced, tstep);
output vtforced, tstep;
voltage vtforced, tstep;

real stepsize, t0, t1;

analog begin
@( initial_step ) begin
t0 = $abstime;
stepsize=10n;
end // initial_step
@( timer(1n) ) stepsize=1000p;
@( timer(2n) ) stepsize=100p;
@( timer(3n) ) stepsize=10p;
@( timer(4n) ) stepsize=1p;
@( timer(5n) ) stepsize=0.1p;
@( timer(6n) ) stepsize=0.01p;
@( timer(7n) ) stepsize=0.001p;

$bound_step( stepsize );
t1 = $abstime;
V(vtforced) <+ stepsize;
V(tstep) <+ t1 - t0;
t0 = t1;
end // analog

endmodule

Title: Re: simulator ignores small values in bound_step()
Post by bobr on Dec 14^th, 2009, 9:06am

Pancho, Thanks for looking at this. I like your addition of "V(tstep) <+ t1 - t0;" to the Verilog-A code.

Unfortunately, my sim still refuses to make the timestep go below 2ps! You can see this in my attached waveforms. Can you tell me what version of HSPICE you use? I'm using version: C-2009.09.

Thanks, Bob[img][/img]

Title: Re: simulator ignores small values in bound_step()
Post by pancho_hideboo on Dec 14^th, 2009, 9:10am

bobr wrote on Dec 14^th, 2009, 9:06am:

Can you tell me what version of HSPICE you use? I'm using version: C-2009.09.

See title of my right graph.
I used C-2009.03 32bit Version.

To my regret, I can not access C-2009.09.

If there is anyone who can access HSPICE C-2009.09, try to run simulation and show us results.

Title: Re: simulator ignores small values in bound_step()
Post by bobr on Dec 14^th, 2009, 10:45am

I ran it in: HSPICE version C-2009.03-SP1
and I see the same result. Could it be something with the Verilog-A compiler version? I use: 1.79.101.011509

Thanks, Bob

Title: Re: simulator ignores small values in bound_step()
Post by pancho_hideboo on Dec 14^th, 2009, 11:28am

My environments are :
****** HSPICE -- C-2009.03 32-BIT (Feb 24 2009) linux ******
hsp-vacomp: Synopsys HSPICE Verilog-A Compiler Version 1.75.100.013009.

Title: Re: simulator ignores small values in bound_step()
Post by bobr on Dec 14^th, 2009, 2:26pm

I ran it in Spectre as well, and it works as expected. Still hitting the 2ps limit in HSPICE. I have a ticket in at Synopsys. I'll let you know if I find out anything.

Thanks for sim-ing it, Bob