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Design >> Analog Design >> PLL Jitter
https://designers-guide.org/forum/YaBB.pl?num=1260736249

Message started by Mayank on Dec 13^th, 2009, 12:30pm

Title: PLL Jitter
Post by Mayank on Dec 13^th, 2009, 12:30pm

Hi all,
I have obtained a graph of overall PLL phase noise in locked state which follows Phase-Detector Noise[CPUMP,PFD,Dividers,Reference noise] before PLL BandWidth & follows VCO noise after PLL BandWidth.

Now my questions are,
1. if I integrate this graph from a low freq(say, 10kHz) to Fosc/2, I get rms Phase Error, right ???
2. if I multiply this rms phase error by T_osc/(2*pi) , I get a Jitter value. Is This particular Jitter ---
a. rms Single-Period Jitter ??
b. rms Cycle-to-Cycle Jitter ??
c. Long-Term or Accumulated Jitter ??

Can anyone clarify this please ?

regards,
Mayank.