The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> Sampling Jitter of ADC ??
https://designers-guide.org/forum/YaBB.pl?num=1260769814

Message started by Mayank on Dec 13^th, 2009, 9:50pm

Title: Sampling Jitter of ADC ??
Post by Mayank on Dec 13^th, 2009, 9:50pm

Hi all,
There's a limit on sampling Jitter of an ADC set by the desired SNR.

1. Can somebody suggest me some good material which explains how do we backcalculate the requirements on jitter of the sampling clock ??

2. The output of this ADC will go directly into BaseBand which takes FFT of this sampled signal. Now FFT is a windowed operation. So, is there a limit on accumulated / long-term jitter of sampling clock also ? OR is it that we are concerned with cycle-to-cycle jitter of the sampling clock ???

thanx,
mayank.

Title: Re: Sampling Jitter of ADC ??
Post by pancho_hideboo on Dec 14^th, 2009, 2:46am

Mayank wrote on Dec 13^th, 2009, 9:50pm:

1. Can somebody suggest me some good material which explains how do we backcalculate the requirements on jitter of the sampling clock ??

The following relation is well known.
SNR=-10*log₁₀[2/(3*2^Nbit) + {2*pi*fin*Tsj/sqrt(2)}²]
Here Nbit=Resolution Bits of ADC, fin=Frequency of Input Signal, Tsj=Peak Value of Sampling Jitter

Search application notes of ADI or TI(Burr Brown)

Mayank wrote on Dec 13^th, 2009, 9:50pm:

Now FFT is a windowed operation.
So, is there a limit on accumulated / long-term jitter of sampling clock also ?

I can't understand a meaning of your question.
Please explain in detail with using correct terminologies.

There are many methods for evaluation of ADC SNR
Most simple method for evaluation of ADC SNR is FFT.
I think answer is self-obvious.

Title: Re: Sampling Jitter of ADC ??
Post by Mayank on Dec 14^th, 2009, 5:26am

Hi Pancho,

Quote:

The following relation is well known.
SNR=-10*log10[2/(3*2Nbit) + {2*pi*fin*Tsj/sqrt(2)}2]
Here Nbit=Resolution Bits of ADC, fin=Frequency of Input Signal, Tsj=Peak Value of Sampling Jitter

I know this formula, BUT my doubt is This T_sjis cycle-to-cycle Jitter of the sampling clock ?? OR is T_sj the long-term k-cycle Jitter of the sampling clock ??

I am designing the PLL for the sampling clock of ADC.
Cycle-to-Cycle Period Jitter depends mostly on VCO+LoopFilter and is not corrected by the PLL. While Long-Term Period Jitter is corrected by the PLL , is dependent on PLL BW & noise contibutions from cpump/pfd/dividers/reference etc.

I want to know this T_sj represents which metric out of these two ?

regards,
Mayank.

Title: Re: Sampling Jitter of ADC ??
Post by raja.cedt on Dec 14^th, 2009, 5:53am

hi mayank,
i feel it's longtem jitter, because in ADC variation in sampling instant will degrade your SNR, so in this regard long term jitter you have to consider. but in your second post i didn't understand ''Cycle-to-Cycle Period Jitter depends mostly on VCO+LoopFilter and is not corrected by the PLL. While Long-Term Period Jitter is corrected by the PLL , is dependent on PLL BW & noise contibutions from cpump/pfd/dividers/reference etc.''

Thanks,
Rajasekhar.

Title: Re: Sampling Jitter of ADC ??
Post by pancho_hideboo on Dec 14^th, 2009, 5:58am

Mayank wrote on Dec 14^th, 2009, 5:26am:

I know this formula,
BUT my doubt is This T_sjis cycle-to-cycle Jitter of the sampling clock ??
OR is T_sj the long-term k-cycle Jitter of the sampling clock ??

None of them.

It is a simple edge-to-edge jitter.

In actual measurement, use reference clock of PLL as trigger signal of oscilloscope.

In EDA Tool Play using small signal noise analysis subjected to large signal steady state analysis,
such absolute jiitter(timing jitter) measurement is possible.
See attached figure of http://www.designers-guide.org/Forum/YaBB.pl?num=1260521995/5#5
I mean "Absolute Jitter" there.

BTW, how do you define "linewidth" in your results of http://www.designers-guide.org/Forum/YaBB.pl?num=1050465395/17#17 ?

Title: Re: Sampling Jitter of ADC ??
Post by Mayank on Dec 14^th, 2009, 7:39am

Hi all,

@ raja :
Quote:

because in ADC variation in sampling instant will degrade your SNR

Two Points :--
1. Variation in each Sampling Instant is Cycle-to-Cycle Jitter.
2. Variation in a Sampling Instant of a Nth Sample wrt to a particular Sample will fall in Long-Term Jitter.

@ Pancho : I would like to mention Sir that i am still in designing Phase...Unfortunately, i dont have any test-chip of my design that i can test for. But i will keep your points in mind when i do actual testing. Coming Back to my query,

Quote:

It is a simple edge-to-edge jitter.

Edge-to-Edge Jitter metric is always used in those circuits which are driven by an external clock,in our case the ADC, whose clock comes from the output clock of my PLL. So, The Cycle-to-Cycle Jitter of the PLL Output Clock forms the Edge-to-Edge Jitter for sampling clock of ADC. Is This opinion Correct ???

Two More Questions :---

Also, The Cycle-to-Cycle Jitter of a PLL is given simply by the VCO + LF Phase Noise, as indicated in Ken's Paper http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf equations (63) & (74) on page on page 31 & 32 respectively. Am i correct ??

When I integrate the output phase noise curve of a PLL & obtain rms phase error & corresponding Jitter in Time domain by multiplying rms Ph. error by Tosc/2/pi , What i get is Long-Term PLL Jitter right ??
This post makes me think i am correct -- http://www.designers-guide.org/Forum/YaBB.pl?num=1236788112/0#5

Quote:

BTW, how do you define "linewidth" in your results of http://www.designers-guide.org/Forum/YaBB.pl?num=1050465395/17#17 ?

This is the Oscillator Line-Width that is indicated by Cadence Spectre in Output Log & also marked as Corner Frequency in a 'Phase Noise' plot in 'pnoise' option of Direct Plot Form....I Just placed a Marker at that Frequency.

--regards,
Mayank.

Title: Re: Sampling Jitter of ADC ??
Post by pancho_hideboo on Dec 14^th, 2009, 7:46am

Mayank wrote on Dec 14^th, 2009, 7:39am:

Not correct.
In actual measurement, we can't define absoulte jitter for free-running VCO.
But we can define absoulte jitter for locked state of PLL.

Title: Re: Sampling Jitter of ADC ??
Post by Mayank on Dec 14^th, 2009, 8:10am

Hi Pancho,

Quote:

In actual measurement, we can't define absoulte jitter for free-running VCO.
But we can define absoulte jitter for locked state of PLL.

I am talking about Locked State of a PLL itself.
Even in the Locked State of a PLL, the Cycle-to-Cycle Jitter is determined by the VCO + LF itself because PLL Loop being slow, say slower than nearly 1000 times the VCO Frequency, cannot correct Cycle-to-Cycle Jitter which is a measure absolute jitter b/w two consecutive time periods.
You can view this as ---> Within PLL BW, PLL Low-Passes & limits Oscillator Jitter. After PLL BW, PLL Phase Noise plot tracks the Oscillator Phase Noise which means that after PLL Loop BW, PLL can't correct the Jiiter
However, PLL can correct long-term jitter which is average Jitter of a Nth edge wrt to a particular edge, because there the slow PLL Loop corrects & maintains Jitter within Bounds.

Quote:

we can't define absoulte jitter for free-running VCO.

By This statement, i understand that you are referring to Long-Term Jitter as absolute Jitter.
Reasoning for my belief - Because in case of a Free-running VCO, Long-Term Jitter goes Unbounded as there's No Loop/Mechanism to Correct it, as is indicated by the inceasing Pnoise with decreasing Freq Offset in a Pnoise Plot of Free-running Osci. But in a PLL, this osci pnoise being low-passed is bounded and you can get a limit on Long-Term Jitter. Correct ??

But Anyways, Cycle-to-Cycle Jitter has nothing to do with Integration/accumulation of Jitter & Hence can still be defined for Both.

--
regards,
Mayank.

Title: Re: Sampling Jitter of ADC ??
Post by pancho_hideboo on Dec 14^th, 2009, 8:21am

Both cycle-to-cycle Jitter and long-term k-cycle Jitter are Self-referred Jitter.
In actual measurement, this is corresponding to self-triggering in oscilloscope.

Jitter in equation of SNR of ADC is a simple absolute jitter(timing jitter).

Again you can measure absoulte jitter(timing jitter) of locked state PLL with reference clock as reference signal.
In actual measurement, this is corresponding to external-triggering in oscilloscope.
Of course, strictly speaking, this is not true(god true) absolute jitter.

Title: Re: Sampling Jitter of ADC ??
Post by Mayank on Dec 14^th, 2009, 8:36am

Hello Pancho,

Point understood and taken.
But then if i know the sampling Jitter requirements for the ADC which acc. to you is the simple Timing Jitter wrt an external/reference frequency, How do i put a spec on PLL output Jitter and which metric should i put a spec on -- Long-Term / Cycle-to-Cycle / Absolute Jitter of a PLL ??

+ How do i measure absolute Jitter in a PLL in simulations / EDA Tool Play :P ?? because i am yet not at fab/test-chip stage.

--Mayank.

Title: Re: Sampling Jitter of ADC ??
Post by pancho_hideboo on Dec 14^th, 2009, 8:44am

Mayank wrote on Dec 14^th, 2009, 8:36am:

+ How do i measure absolute Jitter in a PLL in simulations / EDA Tool Play :P ??

Use Transient Noise Analysis.
Or invoke transient analysis using behavioral model.
You can estimate timing jitter.

Title: Re: Sampling Jitter of ADC ??
Post by ywguo on Dec 14^th, 2009, 11:45am

Hi guys,

I think this is the best discussion I have ever seen about the this topic, jitter measurement of PLL and sampling jitter of ADC.

When I test ADC, the signal generator for clock and input are locked together. I think the primary cause is to keep a coherent sampling in the test. If the two signal sources (for clock and signal) has correlated jitter in long term, they will cancel each other partly.

Pancho said,

Quote:

Again you can measure absoulte jitter(timing jitter) of locked state PLL with reference clock as reference signal.
In actual measurement, this is corresponding to external-triggering in oscilloscope.
Of course, strictly speaking, this is not true(god true) absolute jitter.

No, this is not true absolute jitter. It is more like a tracking jitter. The measured jitter depends on the difference between the reference clock and the PLL output. The big problem is that the tracking jitter isn't what we need in ADC application. In real application, the signal source is not locked to the reference clock of the PLL (sampling clock source). I mean that the input signal is not related to the sampling clock usually. So only absolute jitter (maybe we can call it long-term jitter, too) play his role to affect ADC SNR. Even the real application is not the same as what we do in the test.

:(

Best Regards,
Yawei

Title: Re: Sampling Jitter of ADC ??
Post by pancho_hideboo on Dec 14^th, 2009, 2:49pm

ywguo wrote on Dec 14^th, 2009, 11:45am:

When I test ADC, the signal generator for clock and input are locked together.

Right.

ywguo wrote on Dec 14^th, 2009, 11:45am:

In real application, the signal source is not locked to the reference clock of the PLL (sampling clock source).
I mean that the input signal is not related to the sampling clock usually.

Right.

ywguo wrote on Dec 14^th, 2009, 11:45am:

So only absolute jitter (maybe we can call it long-term jitter, too) play his role to affect ADC SNR.

I don't think a definition of "the long-term k-cycle Jitter" is needed for locked PLL.

ywguo wrote on Dec 14^th, 2009, 11:45am:

The big problem is that the tracking jitter isn't what we need in ADC application.

The tracking jitter might not be proper for ADC evaluation.
But it is useful for ADC's real application where the input signal is not related to the sampling clock,
because the reference in actual system is a reference clock of PLL.
There is no reference other than a reference clock of PLL.

We don't have much confusion about direct Jitter Measurement in Time Domain.
But we have much confusion if we estimate it from Frequency Domain Measurement.

Title: Re: Sampling Jitter of ADC ??
Post by Mayank on Dec 14^th, 2009, 7:22pm

Hello Guys,

So It being said that Absolute Jitter is the correct metric for ADC Sampling clock......How should i compute the absolute Jitter for the PLL, i mean through EDA Tool PLay ??

--
regards,
Mayank

Title: Re: Sampling Jitter of ADC ??
Post by Mayank on Dec 14^th, 2009, 9:10pm

Hi again,
Continuing the Discussion on which metric of Jitter to use while measuring Sampling Jitter for ADC, Professor Boris Murmann from Stanford , in his course VLSI Conditioning Cirtcuits ee315b, seems to tell otherwise. He seems to point that CYCLE-to-CYCLE JITTER is used a metric for Sampling Jitter.
In this pdf [-- lectures/reader of this course]
https://ccnet.stanford.edu/cgi-bin/course.cgi?cc=ee315b&action=handout_download&handout_id=ID125185307612754 ,
On page 98 (lecture 5 slide 31), he gives the formula for SNR due to Aperture Uncertainty, and later in his pdf on page 323 (lecture 19 slide 12), He calculates Cycle-to-Cycle Jitter as a metric for Sampling Jitter.

Any insights ??

@ Pancho & Yawei :-- Also, Why should we Use TRACKING JITTER as a metric for Sampling Clock when we know that the Input Signals has NO CORRELATION Neither to the Reference Clock nor the PLL Output Clock. ??
I Guess using Tracking Jitter to define sampling Jitter is wrong. Instead Cycle-to-Cycle Jitter which will give the ABSOLUTE sampling Jitter between two adjacent samples should be used.

--regards,
Mayank.

Title: Re: Sampling Jitter of ADC ??
Post by ywguo on Dec 17^th, 2009, 12:36pm

Hi Pancho,

pancho_hideboo wrote on Dec 14^th, 2009, 2:49pm:

ywguo wrote on Dec 14^th, 2009, 11:45am:

So only absolute jitter (maybe we can call it long-term jitter, too) play his role to affect ADC SNR.

I don't think a definition of "the long-term k-cycle Jitter" is needed for locked PLL.

Take account of the closed loop behavior of PLL, the k-cycle jitter will approach a constant after k cycles. The number k is determined by the time constant (GBW) of the PLL. Is it the reason why you said that a definition of "the long-term k-cycle jitter" is not needed for locked PLL?

pancho_hideboo wrote on Dec 14^th, 2009, 2:49pm:

We don't have much confusion about direct Jitter Measurement in Time Domain.
But we have much confusion if we estimate it from Frequency Domain Measurement.

What do you mean that we have much confusion if we estimate it from Frequency Domain Measurement? In EDA tool?

Best Regards,
Yawei

Title: Re: Sampling Jitter of ADC ??
Post by Mayank on Dec 19^th, 2009, 12:55am

hi yawei,

Quote:

Take account of the closed loop behavior of PLL, the k-cycle jitter will approach a constant after k cycles. The number k is determined by the time constant (GBW) of the PLL.

I agree to the fullest.

Quote:

What do you mean that we have much confusion if we estimate it from Frequency Domain Measurement? In EDA tool?

I also have the same confusion of converting phase noise PSD in Freq Domain to Jitter in Time Domain. I think Pancho was pointing to this confusion.
My Explanation --
1. How to set limits of integration in Freq Domain for integrating PLL Phase Noise plot (which follows PD b4 BW & VCO after BW) to obtain Jitter ??
2. And I believe the metric(cycle-2-cycle / long-term period jitter) of this Jitter obtained through this method depends upon the Limits ofIntegration.
3. According to me, If you integrate your PLL phase noise Plot ,
a.> From a very low freq( by low i mean below Linewidth of Osci) to Fosc/2 -- The Phase Noise plot is no longer Lorentzian below Linewidth & that Phase noise is because of Flicker Noise. The Jitter that we calculate by this integration will give us the Long-Term k-cycle Period Jitter including the Slow Drift/Wander in the PLL Output.
b.> From a Freq above linewidth to Fosc/2 -- The Phase Noise plot is totally Lorentzian. & The Jitter that we will get through this integration would indicate Long-Term k-cycle Period Jitter without any effects of Drift / Wander Included.
c.> Cycle-to-Cycle Jitter -- Pnoise value at an offset greater than Linewidth, where Lorentzian assumption holds true, when converted to time domain through Lorentzian small signal assumption frmula gives C-2-C Jitter. Here, we dont integrate because we are considering adjacent Cycle Jitter. Integration means memory effects means Long-Term Jitter.

Pls feel free to comment [ /compliment ;) ]

Title: Re: Sampling Jitter of ADC ??
Post by Frank Wiedmann on Dec 19^th, 2009, 2:31am

Without additional assumptions, only strobed noise can be converted to jitter. You can find the formula at http://www.designers-guide.org/Forum/YaBB.pl?num=1224609785/9#9.

Title: Re: Sampling Jitter of ADC ??
Post by Berti on Feb 4^th, 2010, 12:06am

Hi all,

Interesting discussion but I think it misses the answer to the original question.

I would approach the problem in a different way:

What you get in the ADC output spectrum basically results from reciprocal mixing between the ADC input signal and the phase noise of your clock. The problem is however that for ADC the required jitter is typically specified as jitter, while for PLL/VCO design it is more convenient to know the required phase noise. Demir has published a couple of papers where phase noise of a PLLs is related to jitter. These equations use cycle jitter (self-referred) as the equation should remain valid as the PLL loop bandwidth goes towards zero. But that no problem at all because as long as the clock frequency is much larger than the PLL loop bandwidth: Jc ≈ √2×Jee (Jc : cycle Jitter, Jee : edge-to-edge Jitter).

That means:

1.) Use the simple formula the estimate the required Jee.
2.) Calculate Jc and translate that into phase noise requirements.
3.) Start designing your PLL.
4.) Once you can use simulations (pnoise), the simulator can calculated the desired jitter metric for you.

Regards

Title: Re: Sampling Jitter of ADC ??
Post by David Lee on Feb 6^th, 2010, 10:29am

Classically, aperture jitter (absolute jitter) is used for evaluating ADC's SNR.

However, suppose you plan to differentiate the waveform, i.e. take the difference of every two adjacent samples. Then use period jitter.

Suppose you plan to take the sum of every two samples that are eight samples apart. Then use 8-period jitter.

In real life, which jitter metric (absolute jitter, period jitter, cycle to cycle jitter - aka adjacent period jitter, etc.) matters is a function of the actual data processing to be done on the data samples, and is circuit dependent.

David.

Title: Re: Sampling Jitter of ADC ??
Post by Berti on Feb 7^th, 2010, 11:58pm

Hi David,

You are right, but I think you miss the point.
The jitter specifications obtained for the ADC need to be related to the clock source. In the case of a PLL phase noise specifications are required for block level design. In this case, aperture jitter is typically not very useful....unless you solely rely on simulations.

Cheers