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Design Languages >> Verilog-AMS >> how to perform multiple assignments on case statement
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Message started by Ari on Dec 15^th, 2009, 11:52am

Title: how to perform multiple assignments on case statement
Post by Ari on Dec 15^th, 2009, 11:52am

Hi,

I wish to perform several assignment to variable on each case of my case statement. i.e.:
@(timer(tstart, period)) begin
case(rnd )
( 0 ) : a=0;
b=1;
c=3;
( 1 ) : a=3;
b=1;
c=2;
endcase

However, compiler reject such syntax (or alike), and I don't see any example for for multiple assignments, or and specification for this in the 2.3 LRM

Does anyone know if syntax supports multiple assignments?

Thanks in advance,

Ari

Title: Re: how to perform multiple assignments on case statement
Post by Ken Kundert on Dec 15^th, 2009, 11:57am

make them a single statement by surrounding them with begin/end.

-Ken

Title: Re: how to perform multiple assignments on case statement
Post by Ari on Dec 16^th, 2009, 1:46pm

Ken,

Thanks. I missed the possibility :)

Ari