The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> poly orientation in lay-out
https://designers-guide.org/forum/YaBB.pl?num=1261313903

Message started by Dipankar on Dec 20^th, 2009, 4:58am

Title: poly orientation in lay-out
Post by Dipankar on Dec 20^th, 2009, 4:58am

Dear All,
During lay out should we care about uniformity of poly orientation in advanced process nodes like n40? If yes then what should be the major criteria to check out ?

case 1 : you can keep all your mosfets' gate along y direction and all the poly resistors along x direction. This will make sure the current flow through all the devices in x direction.

case 2 : you keep both mosfets' gate and poly resistors along y then you have currents in mosfets (drain to sorce) in x direction but through resistors in y direction. But from uniformity of stress point of view case 2 will be better.

Any thumb rule or standard practice regarding this issue ????

Title: Re: poly orientation in lay-out
Post by loose-electron on Dec 22^nd, 2009, 10:09pm

I would align (same orientation) any resistors that need to match or track each other over process.

In a similar manner, I would use the same orientation of any MOS devices which need to match as well.

Other than that, use good symmetry in layout, centroids where possible, larger than minimum geometry methods, etc. for good matching of devices.

Orientation of the poly gate stripes and the poly resistor stripes probably don't have a lot to do with each other, except where the physical design rules may restrict spacing or orientation.

Title: Re: poly orientation in lay-out
Post by thechopper on Dec 24^th, 2009, 6:42am

I agree with Jerry's comments.

Just consider different stress profiles in the package that will affect differently your poly res if they are placed in different directions.
Same happens with MOS and with other different gradients affecting your devices (temperature for example).

Best
Tosei

Title: Re: poly orientation in lay-out
Post by vivkr on Jan 4^th, 2010, 1:57am

loose-electron wrote on Dec 22^nd, 2009, 10:09pm:

Orientation of the poly gate stripes and the poly resistor stripes probably don't have a lot to do with each other, except where the physical design rules may restrict spacing or orientation.

Exactly! also consider that gate poly is a different animal than poly used for making resistors etc. Gate poly is far thinner than poly laid out on the field oxide. And there should be no reason to try and match gate poly to poly resistors.

Vivek

Title: Re: poly orientation in lay-out
Post by loose-electron on Jan 5^th, 2010, 1:51pm

gate poly tends to be silicided. Usually 1-5 ohms/square

resistor poly is generally not silicided, and tends to be 50-300 ohms/square

(particulars depend on the foundry process of interest)

Now a question for those with TWO propellers on their Beanie Cap:

What's the differnece between a silicided process layer and a SALicided process? :-?

I will be truly impressed if you can answer this one without researching it. 8-)

Title: Re: poly orientation in lay-out
Post by vivkr on Jan 6^th, 2010, 3:10am

loose-electron wrote on Jan 5^th, 2010, 1:51pm:

I don't think there is anything like "salicide". You've got the silicide layer on top of gate poly to lower the resistivity. This is called salicide.

Vivek

Title: Re: poly orientation in lay-out
Post by Mayank on Jan 6^th, 2010, 5:02am

Hi Jerry,

I have come across the term "SALicide Process" and as far as i remember,it is usually used in poly layers making ohmic contacts like gate poly or routing poly.
Precision Poly Resistors are usually mentioned as "SALicide blocked" in DRMs.
At a contact / metal-Si Junction, metal layer reacts with poly-silicon to form a metal Silicide.
And according to my memory, SALicide is just a name for a way of etching/laying out/lithographing this metal silicide on poly-silicon. Processed allowing such lithography are called SALicide processes.
& Sorry, I forgot the full-form of the acronym 'SAL' in SALicide.

--
Mayank

Title: Re: poly orientation in lay-out
Post by Andrew Beckett on Jan 6^th, 2010, 7:52am

http://en.wikipedia.org/wiki/Salicide

Title: Re: poly orientation in lay-out
Post by loose-electron on Jan 6^th, 2010, 4:50pm

LOL - Andrew went to Wikipedia...

A "silicide" is pretty well defined here:

http://en.wikipedia.org/wiki/Silicide

In a nutshell it is a class or grouping of chemical processes that involve silicon. Most chip designers think of it as a way to reduce the gate polysilicon resistance, but its actually a bit more than that.

A "SALicided process" is a little bit of a bastard - The original definition is an acronym that came out of IBM as a "Self Aligned Integrated Circuit Process"

The SALICided process came about when CMOS evolved away from metal gates, the gate poly was defined and the field oxide was defined, and those two items served as the alignment for the definition of the drain and source, which got diffused (nowadayus ion implanted) by using the gate poly and the field oxide as a mask for those D & S implants. which are done though the gate oxide.

It allowed the elimination of overlap regions and reduction of stray capacitance.

That and $ gets me coffee.... :D

Jerry

Title: Re: poly orientation in lay-out
Post by loose-electron on Jan 6^th, 2010, 4:55pm

Mayank wrote on Jan 6^th, 2010, 5:02am:

Precision Poly Resistors are usually mentioned as "SALicide blocked" in DRMs.
Mayank

The salicide term gets used incorrectly in a lot of places - TSMC does it wrong in a bunch of their documents as well.

The gate polysilicon is typically silicided to reduce resistance. The Poly resistor is "silicide blocked/removed" not salicide.

Title: Re: poly orientation in lay-out
Post by ywguo on Jan 11^th, 2010, 9:54pm

Hi Jerry,

Interesting question. In some old processes, like Chartered 0.35um CMOS, there is a name polyside. I think that means only poly (including gate poly and resistor poly) is silicide. For SAlicide process, the poly and active area (drain and source) are silicide. The self alignment is done by the spacer at the edge of poly gate. The space is often made of oxide (including silicon dioxide and Nitride) which cannot become silicide. Am I right?

Best Regards,
Yawei

Title: Re: poly orientation in lay-out
Post by Mayank on Jan 11^th, 2010, 11:00pm

Hi Jerry,

Quote:

Precision Poly Resistors are usually mentioned as "SALicide blocked" in DRMs.
Mayank

I was referring to chartered 65 DRM. It clearly mentions that for resistors, they use an additional mask to block SALicidation. They might just be wrong, like tsmc as you said.

But isn't silicide when laid out through self-alignment process (which you explained in your earlier post) referred to as SALicide ??
Then i guess, Afterall both tsmc and chartered are correct in referring to silicidation of gate poly as SALicidation and to poly resistors as " SALicide blocked " instead of silicide blocked. :P

--
Mayank.

Title: Re: poly orientation in lay-out
Post by loose-electron on Jan 30^th, 2010, 11:29am

Like I said - the terms get scrambled up a lot and get used incorrectly.

Go read the above on Silicides, - I have seen the term "polycide" (and other equally strange terms) used in various foundry documents as well. You need to go to the foundry to get the specifics of what they are really doing. In a lot of cases they made up a name for something they are doing, and that's fine. You invent it, you get to name it.

But then, here in the USA what gets created at Taco Bell (and their strange names) doesn't exist in Mexico.

Also, last I checked, the "Chinese Fortune Cookie" is very much an American invention and has nothing to do with China.

For those of you in the far east:
http://www.chinese-fortune-cookie.com/

Silicide? Salicide? Polycide? "Super Deep N-Well Trench Technology" and many other terms are used without a science basis and largely get created in the marketing department, not engineering.

Title: Re: poly orientation in lay-out
Post by loose-electron on Jan 30^th, 2010, 11:32am

ywguo wrote on Jan 11^th, 2010, 9:54pm:

Not too sure - would have to look at the details of the foundry process to find out whats going on. A lot of that information is generally not available to the the circuit desinger.

Title: Re: poly orientation in lay-out
Post by Berti on Feb 2^nd, 2010, 5:22am

Hi Guys,

I have another related question/comment. Keeping poly orientation for matching is clear.
But for advanced processes (45nm and below) quite different transistor behavior (±20%) has been reported depending on the transistor orientation (related to the orientation of the crystal lattice of substrate).
Does anybody have experience in this area? Is that already checked by design rules in these technologies? DFM?

Cheers

Title: Re: poly orientation in lay-out
Post by Mayank on Feb 2^nd, 2010, 6:26am

Hi Berti,

Quote:

But for advanced processes (45nm and below) quite different transistor behavior (±20%) has been reported depending on the transistor orientation (related to the orientation of the crystal lattice of substrate).

Generally 111 lattice orientation is considered the best substrate orientation to align the transistor channel. The stress and atom density is least along this direction, hence increased mobility.
I think we just need to align transistor directions in layout. Fabricator himself takes care to fab it in that alignment.

--
Mayank.

Title: Re: poly orientation in lay-out
Post by Berti on Feb 2^nd, 2010, 7:04am

Hi Mayank

Quote:

Generally 111 lattice orientation is considered the best substrate orientation to align the transistor channel.

I think in most recent technologies people switched to <100> ...

Quote:

Fabricator himself takes care to fab it in that alignment.

Sure, but in a typical SoC not all the transistors have the same orientation?
Should that design practice be reconsidered for <65nm or do DRC/DFM not even allow different poly orientations?

Cheers