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Design >> RF Design >> how to minimize the bias circuit's effect to LC VCO's phase noise
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Message started by anny on Dec 20^th, 2009, 5:57am

Title: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by anny on Dec 20^th, 2009, 5:57am

hi all,
I need design a 1.4GHz VCO using 0.13um CMOS process. I find that with ideal tail current, the larger current the phase noise is better, however, when I add the current bias circuit, phase noise degenerate much. how to optimize the current? how the bias current affect the VCO's phase noise?
thanks!

Title: Re: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by raja.cedt on Dec 21^st, 2009, 5:46am

hi,
can you post the schematic..is it LC vco or ring?

Thanks,
rajasekhar.

Title: Re: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by wave on Dec 22^nd, 2009, 1:52pm

Your phase noise analysis is picking up the Bias circuitry. That is a real issue. You may need to re-design the bias for lower noises (1/f, thermal). The max I should maximize the oscillator amplitude, no more. You are trapped between maximizing signal and minimizing noise

--- at the moment it seems like adding current adds more noise than signal, which means your bias is the limiting factor.

8-)

Title: Re: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by raja.cedt on Dec 22^nd, 2009, 8:26pm

hi anny,
as wave said bias noise has lot of impact on overal phase noise,even though it's magnitude is less due AM to PM conversion and 1/f up conversion you will end up with huge amount of PN. you can refere the following papa to get some idea.

'The Impact of Device Type and Sizing on Phase Noise Mechanisms'

Thanks,
Rajasekhar.

Title: Re: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by loose-electron on Dec 26^th, 2009, 4:10pm

run a noise analysis on the bias circuits and find out what the sources are. In a similar manner to how you would on a reciever signal processing chain.

Adjust geometries/current accordingly.

As a start point, put an ideal voltage source controlling the bias of the current source. If you can't get teh current source (minus all the bias control circuits) quiet enough, you need to rethink the architecture.

Also - sometimes you can reduce the BW of the noise by passive methods, (filter the bias) and suppress the low frequewncy part by feedback methods.

lots of possible options

Title: Re: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by Mayank on Dec 27^th, 2009, 5:48am

Hi

@ Anny :
I agree with Jerry's suggestion on passive filtering. I have also used it to reduce Noise BW...

@ Jerry : can you pls. elaborate a bit more on
Quote:

suppress the low frequency part by feedback methods.

Can you suggest some references on this kinda noise suppression by feedback in bias ckts. ??

& btw, hope u had a Merry Christmas !! :)

thanx,
Mayank.

Title: Re: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by RFrequency on Dec 30^th, 2009, 9:22am

A filtering technique to lower LC oscillator phase noise, JSSC, from Abidi. This paper is the most famous one for noise filtering.

Mayank wrote on Dec 27^th, 2009, 5:48am:

Hi

@ Anny :
I agree with Jerry's suggestion on passive filtering. I have also used it to reduce Noise BW...

@ Jerry : can you pls. elaborate a bit more on
Quote:

suppress the low frequency part by feedback methods.

Can you suggest some references on this kinda noise suppression by feedback in bias ckts. ??

& btw, hope u had a Merry Christmas !! :)

thanx,
Mayank.

Title: Re: how to minimize the bias circuit's effect to LC VCO's phase noise
Post by rfcooltools.com on Jan 2^nd, 2010, 11:50pm

If your bias is broadband ie contributes noticeable noise at 1xLO and 2xLO etc then these noise sources will either feed through or be harmonically converted. Then in this case filtering of the bias will help, additionally you may externally regulate (external since cap on chip usually is prohibitively large), you may be able to knock down the 0XLO related noise or atleast push them low enough to be reduced by the PLL loop.

Also,
Consider a differential GM type of oscillator, a considerable amount of noise can be attributed to 2xLO and other even order harmonic mixing at the common source. This often gets worse when the current increases due to the impedence being lowered at the common source. This is commonly eliminated by adding a resistor or some frequency selective high impedance circuit such as a LC tank.
Finally,
VCO phase noise improves when the voltage of the oscilation increases and not only the current increases, If you increase the current and the amplitude of the oscilation only slightly increases then phase can be worse not better.