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Design >> Analog Design >> Loop gain on the flip around SHA
https://designers-guide.org/forum/YaBB.pl?num=1261367547

Message started by nobody on Dec 20^th, 2009, 7:52pm

Title: Loop gain on the flip around SHA
Post by nobody on Dec 20^th, 2009, 7:52pm

There are two plots and here is the first plot called "charge transfered SHA " In this plot, big resistors are added in parallel with Cs for dc biasing. Sorry for the wrong plot.

Title: Re: Loop gain on the flip around SHA
Post by nobody on Dec 20^th, 2009, 9:15pm

Here is the second plot called "flip around SHA".
The OTA used in the 1st and 2nd plot is the same.
Given the gain of a OTA is A0 ,Cs = 2Cf, and input parasitic capacitance Cpi. Loop gain(1st) is A0*Cf/(Cs+Cf)= 1/3*A0
Loop gain(2nd) is expected to be A0*Cf/(Cf+Cpi).
I can simulate the loop gain correctly in the 1st plot by using hspice
but fail to get the loop gain in in the 2nd plot. I would like to konw what goes wrong. The ideal CMFB(VCCS) is added and ideal baluns are added to convert differential and common signals.

Thanks a lot.