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Design >> Analog Design >> very strange problem need help, pls
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Message started by lhlbluesky_lhl on Jan 7^th, 2010, 4:38am

Title: very strange problem need help, pls
Post by lhlbluesky_lhl on Jan 7^th, 2010, 4:38am

have designed a SH(sample-holde) circuit, just as the picture shows (fig1). it consisits of four TG and two Buffer, IN is a changing signal, first, S1 is on, and IN is stored in C1 (just called IN1), then, S2 is on, IN (has changed) is stored in C2 (IN2). after a while, S3,S4 on at the same time, readout the difference of IN1 and IN2 (fig2). that is, S3 and S4 are the same signal.

originally, i use S3 and S4 for different ports in layout, and i add stimilus in the four ports, of course, S3 and S4 have the same stimilus, S3- and S4- have the same stimilus, and the simulation result is ok (12 bit resolution). while i want to connect S3 and s4, S3- and S4- together separately in layout, so only two ports needed. however, when rerun the simulation, the result is very bad, very different, only 8 bit resolution.

i'm sure that, i only connect them together in layout with a short wire (fig3), nothing else. but why? why does the resolution have such a big reduction? i cheched my layout, except the two connecting wire, no other change has made. but the simulation result is very strange, can any one help me? thanks all.

in fig3, only two stimilus added, one for S3(S4), one for S3-(S4-). i really need your help, thanks.

and after i connect S3 and S4, S3- and S4-, the simulation result shows that, the resolution decline starts at the node after the first switch (that is, the positive end of buffer), but i have not changed that part, i only added the two short wire as fig3 shows. it is very strange, why?

Title: Re: very strange problem need help, pls
Post by lhlbluesky_lhl on Jan 8^th, 2010, 6:34am

can anyone help me? thanks all.

Title: Re: very strange problem need help, pls
Post by loose-electron on Jan 8^th, 2010, 1:25pm

can you attach a jpg or png type picture please? The winzip file did not open for me.

Title: Re: very strange problem need help, pls
Post by Mayank on Jan 8^th, 2010, 8:10pm

Hi bluesky,
Seems like opamp misfunctioning on connecting S3 & S4 / S3- & S4- .....Maybe, when you are connecting the gates of two TG's , the Cgs & Cgd caps at the opamp o/p node get added. This in turn might cause some foul play with your opamp's freq. response like decrease your opamp BW etc. Check if this is happening ? Run it again at schematic level with parasitic + interconnect caps included at these nodes.....If error shows up there, means it's not a layout issue after all.

--
Mayank.

Title: Re: very strange problem need help, pls
Post by lhlbluesky_lhl on Jan 10^th, 2010, 5:47am

i checked the opamp, and it can work well when i connect S3,S4 and S3-,S4- together. are there any other reasons?

the following is the picture.

Title: Re: very strange problem need help, pls
Post by Mayank on Jan 10^th, 2010, 9:08pm

Hi bluesky,
Does it work fine in schematic after connecting S3 & S4 / S3- & S4- ?? Atleast that would clear out whether it's a layout issue or a schematic one....

Title: Re: very strange problem need help, pls
Post by lhlbluesky_lhl on Jan 11^th, 2010, 3:54am

it works fine in schematic after connecting S3 & S4 / S3- & S4-, so i think it is a layout issue. but i don't which parasitic cap or res causes this problem. pls help me. thanks.

Title: Re: very strange problem need help, pls
Post by Mayank on Jan 11^th, 2010, 5:36am

Hi bluesky,
Well our differential says --1. schematic works fine
2. opamps are responding correctly with parasitic caps too both in layout and schematic...

I hope your LVS is correct....

Can you pls. attach you output waveforms with and without S3/S4 connections ??

--
Mayank.

Title: Re: very strange problem need help, pls
Post by lhlbluesky_lhl on Jan 12^th, 2010, 4:37am

the output waveform is just the same, except that (for the same input)the resolution in the positive end of opamp has a big reduction. why? any possible reasons?