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Design >> Analog Design >> help regarding digital error correction in pipeline adc
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Message started by yvkrishna on Jan 11^th, 2010, 1:28am

Title: help regarding digital error correction in pipeline adc
Post by yvkrishna on Jan 11^th, 2010, 1:28am

Hi,
I am new to pipeline adc design, can some one help me in understanding digital error correction in detail,
I have read that it relaxes the comparator offset spec but could not understand how exactly it does.

any inputs/references?

Regards
yvkrishna

Title: Re: help regarding digital error correction in pipeline adc
Post by vivkr on Jan 12^th, 2010, 5:39am

yvkrishna wrote on Jan 11^th, 2010, 1:28am:

You mean digital redundancy. Unfortunately, the term "error correction" is used here. Digital redundancy is achieved by limiting the swing of the residue amplifier to half of the full scale range (+/- FS/2) around the comparator decision points, thereby ensuring that the smallest comparator offset does not push the residue outside the specified input range for the ADC.

The details cannot be discussed in a forum. Try reading up some papers. I can recommend the following:

1. Lewis, Gray, JSSC, Dec. 1987

2. Ginetti, Jespers, JSSC, Jul. 1992

There are tons of Ph.D theses on pipelined ADCs from Paul Gray's group which all discuss the concept to differing levels of detail, but maybe it is best to just read the papers.

Be prepared to spend a lot of time figuring out the concepts by yourself as the papers alone will not be enough.

Vivek

Title: Re: help regarding digital error correction in pipeline adc
Post by yvkrishna on Jan 12^th, 2010, 11:01pm

thanks for the reply.