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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> question on self biased opamp https://designers-guide.org/forum/YaBB.pl?num=1263289463 Message started by yvkrishna on Jan 12th, 2010, 1:44am |
Title: question on self biased opamp Post by yvkrishna on Jan 12th, 2010, 1:44am what is the advantage/disadvantage of using a self biased opamp ? this structure shown in the fig is commonly used as an error amp in the bandgap voltage ref circuits, but this self biasing adds one more positive feedback (which complicates the stabilty). So is there any major reason/advantage for using self bias in terms of systematic offset/temperature dependence?? regards, yvkrishna |
Title: Re: question on self biased opamp Post by rf-design on Jan 15th, 2010, 4:22pm If I make a quick guess on this circuit: N4 will have a significant higher threshold voltage because of the substrate effect. So the bias current will be limited by the sum of the threshold voltage of P3 plus saturation voltage of P3 and N3. So bias current is strongly dependend on supply. To get a bias current higher than zero the current loop gain should be higher than 1. So the bias current is set when the gain is equal to 1. So only if N3 goes into LIN mode the bias current is defined. So you have to dimension N3 with a little higher Vdsat to balance N1&N2. I would use a supply independend bias. |
Title: Re: question on self biased opamp Post by raja.cedt on Jan 17th, 2010, 8:39am @vamis: eventhough it is a self bias circuit that doesn't mean it complicates stability (i am assuming that you are using this opamp for some other purpose, so that if you keep your main loopgain keep the ckt functions properly)howerver this +ve feedback gives startup troubles some time. Comming to the importance of the circuit it is mainly to track the system poles with load current and it will give higher dc gain also. But can you please tell me why N$ is nmos, i guess it is Pmos. @rf: I agree with you for supply dependent bias current, but due self bias it will operate at desired oparating point and could you please ecplain 2nd half of your post. Thanks, Rajasekhar. |
Title: Re: question on self biased opamp Post by Mayank on Jan 17th, 2010, 10:30am Hi, @ raja : Quote:
Quote:
@ rf-design : Quote:
The diode connected nmos load N2 generates N3's bias, which in turn generates P3's bias, which is mirrored back into Tail Current Source P0. To get a bias current higher than zero the current loop gain should be higher than 1 The Loop's a +ve feedback one....If the loop gain, be it current or voltage, is higher than 1, it would be unstable....A Startup ckt is needed to avoid 0 Bias Current meta-stable condition. -- Mayank. |
Title: Re: question on self biased opamp Post by raja.cedt on Jan 17th, 2010, 8:05pm hi mayank, it is a replica based self bias, so N4 is mainly to replicate pmos diff pair transistor, so i guess it should be pmos and gate may go to ground. Thanks, Rajasekhar. |
Title: Re: question on self biased opamp Post by Mayank on Jan 17th, 2010, 8:55pm Hi, Quote:
Here, instead we are just connecting a resistance in b/w to create some vds across it.... A nMOS with VDDed gate should serve as good as a pMOS with GNDed Gate. -- Mayank. |
Title: Re: question on self biased opamp Post by yvkrishna on Jan 17th, 2010, 11:40pm Thanks for the replies guys. I agree with mayank, the presence of nmos if just to create some vds drop there.. at the same time as raja questioned pmos would have been more suitable there. Just to confirm are you guys pointing out the presence of nmos/pmos would help in reducing the systematic offset ?? @rf-design as mayank pointed out i feel N3 should not be in linear also since loop is positive one,its loopgain should have been <1 to avoid unstabilty. please clarify about the statement: ""To get a bias current higher than zero the current loop gain should be higher than 1. So the bias current is set when the gain is equal to 1"" @mayank just out of curiosity ..Is it fine if we can make the total loop gain of the system negative (assume a bandgap ckt with other loops +ve and -ve) even with the loopgain of this selfbias loop >1; Guys finally I have a doubt about placement of additional pole in this self bias loop ..(taking into account of the startup/stabilty...) will this pole be present exactly at the same location the total transfer function?? (assume this opamp is used in a bandgap circuit) so is it just enough to place this place from loop's UGBW for sufficient phase margin?? I have this question because I observed problems with startup while simulating in which i havent took care of this pole location... many thanks for your suggestions/comments. regards, yvkrishna |
Title: Re: question on self biased opamp Post by loose-electron on Jan 18th, 2010, 10:11am In a sentence -- Why bother? It's an op-amp - keep it simple and use a reference current if its available from the system, or if it has to be stand alone, use a resistor to set the current. Put a LPF capacitor on the bias line to keep power noise off the bias and you are done. Yes it will vary with power supply, resistor variance, temperature, but if you keep the gain & BW high enough in all corners its not going to matter a whole lot. Sorry - but I dislike fancy stuff where its not needed. Just one more thing to fail, or cause problems later on. No problem where its needed, but biasing an op-amp is not one of them. |
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