The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> Error in AMS simulation
https://designers-guide.org/forum/YaBB.pl?num=1263356984

Message started by VINAY RAO on Jan 12^th, 2010, 8:29pm

Title: Error in AMS simulation
Post by VINAY RAO on Jan 12^th, 2010, 8:29pm

Hi,
I have 2 blocks,one is verilog-A (comparator) module and another is verilog (digital decoder) module. It is actually a conventional flash ADC. I am directly connecting output of verilog-A to verilog module and i modified built-in connect rules.Since my supply voltage is 3.3v, i modified built-in "connectLib.ConnRules_18v_full_fast" which is in ConnectLib library and renamed it as "ConnRules_33v_myrule_fast". I changed "vsupp" to 3.3v , vthi=1.75v , vtlo=1.55,where both vthi and vtlo having equal deviation of 0.1 from (vsupl/2).I am using ic5141 and ius8.2. Design is compiling succesfully but giving error during elaboration.Error are as..

Elaborating the design hierarchy:ncelab: *N,SFEDPL: Deploying new SFE in analog engine. Discipline resolution Pass... Doing auto-insertion of connection elements... Building instance overlay tables: ....ncelab: *F,INTERR: INTERNAL ERROR-----------------------------------------------------------------The tool has encountered an unexpected condition and must exit.Contact Cadence Design Systems customer support about thisproblem and provide enough information to help us reproduce it,including the logfile that contains this error message. TOOL: ncelab 08.20-s017 HOSTNAME: vlsi6 OPERATING SYSTEM: Linux 2.6.9-67.0.7.ELsmp #1 SMP Wed Feb 27 04:47:23 EST 2008 x86_64 MESSAGE: sv_seghandler - trapno -1-----------------------------------------------------------------ncelab: Memory Usage - 20.8M program + 609.5M data = 630.4M totalncelab: CPU Usage - 0.0s system + 0.1s user = 0.1s total (0.3s, 45.6% cpu)Failed to elaborate ("vin_proj" "twobmode" "config").

In netlists,its not showing any modified values, vsupl remained to be 1.8v and also other parameters remained to be that of built in rules only.The procedure i followed for modifying the built-in rules is as it is given in a manuel ,here i attached only the doc of procedure. I also attached simulation log file and netlist file.Thank you..

Title: Re: Error in AMS simulation
Post by mikro on Jan 13^th, 2010, 12:45pm

Have you just modifed the connectLib and compiled them in command line ?
Try to do this in Framework (start icfb, build block views for verilog/verilogams modules, change the connectLib in ADE -> connect models). Then the voltage level should be able to be changed to 3.3v.

Title: Re: Error in AMS simulation
Post by VINAY RAO on Jan 19^th, 2010, 9:28pm

Hi,
I changed the values in connect models in ADE itself..But its of the same as that of default values.

Title: Re: Error in AMS simulation
Post by Riad KACED on Mar 3^rd, 2010, 11:18pm

Hi,

Can you make a tarball of your Cadence database and share it if not confidential ? you may contact Cadence otherwise.

You may try to delete the pak/snapshot files and rerun in case corrupted data is hanging around.

BTW, do you run OSS-irun or Cell-Based Netlisting.
Also, you don't need to put your netlist/log files into MS word format, just leave them in plain ASCII, that's easier et quicker to read through.

Regards,
Riad.