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Design >> Mixed-Signal Design >> Measured Id-Vg being much different from simultions
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Message started by cmos.analogvala on Jan 14^th, 2010, 8:09pm

Title: Measured Id-Vg being much different from simultions
Post by cmos.analogvala on Jan 14^th, 2010, 8:09pm

All,
We have recently fabricated our first chip. I measured Id-Vg of the device with gate and drain shorted. This diode connected PMOS' Id-vg's gate terminal taken out to pad thru ESD and it's source is also taken out thru ESD. Now, when I keep its Vsource=1.8V and Vgate=1.8, I see current coming out of source terminal !!! In other words I observe PMOS conducting in opposite direction when VD=VD=VS=1.8 for a 0.18u nominal Vt device !!

Any clues why so ?

-CA

Title: Re: Measured Id-Vg being much different from simultions
Post by pancho_hideboo on Jan 15^th, 2010, 1:18am

cmos.analogvala wrote on Jan 14^th, 2010, 8:09pm:

Now, when I keep its Vsource=1.8V and Vgate=1.8,
I see current coming out of source terminal !!!

How do you treat P-substrate and N-well of PMOS ?

Title: Re: Measured Id-Vg being much different from simultions
Post by cmos.analogvala on Jan 15^th, 2010, 9:32pm

Nwell is connected to VS=1.8 of PMOS and P-substrate of the die is connected to gnd.

Nwell and p-substrate form a reverse biased diode. There are indeed many Nwell contacts to VS=1.8 around the PMOS under test.

Anything wrong in this ?

-CA

Title: Re: Measured Id-Vg being much different from simultions
Post by pancho_hideboo on Jan 15^th, 2010, 9:47pm

How do you connect a instrument to DUT, regarding positive terminal and negative terminal of instrument ?
What instrument do you use ?

Title: Re: Measured Id-Vg being much different from simultions
Post by cmos.analogvala on Jan 17^th, 2010, 8:52am

Measuring Unit is Source Measure Unit which sources voltage and measures current. Positive terminal of the SMU is connected to VG =VD of the terminal. This VG=VD is sweeped from 0 to 1.8 V. Also, positive terminal of a power supply is connected to source node of the PMOS Gnd of both SMU and power supply are connected together to the GND (substrate) of the Chip. NWell of the PMOS is connected to it's source node.

-CA

Title: Re: Measured Id-Vg being much different from simultions
Post by pancho_hideboo on Jan 18^th, 2010, 3:58am

Confirm current flow direction(polarity) of your SMU using simple resistor having two terminals.

Which direction is positive, source current or sink current ?

Title: Re: Measured Id-Vg being much different from simultions
Post by loose-electron on Jan 18^th, 2010, 10:17am

1. Magnitude of current??
2. CMOS feature size??
3. Temperature dependence?
4. Has the system been calibrated and check for I = 0 with nothing connected?
5. Diodes (ESD protection) do exhibit small current leakage in reverse bias.
6. Small feature CMOS (smaller than 0.18uM) all have gate leakage current.

Need some number before you can say whats going on.
Jerry