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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Setting voltage in "static" analysis, in keeping it in transient analysis https://designers-guide.org/forum/YaBB.pl?num=1263850626 Message started by Ari on Jan 18th, 2010, 1:37pm |
Title: Setting voltage in "static" analysis, in keeping it in transient analysis Post by Ari on Jan 18th, 2010, 1:37pm I have VGA (Variable Gain Amp.) which I would like to automatically tune to get specific gain across all corners and conditions. The gain control voltage vctrl should be set during the operating point analysis ("static" analysis) and later on it should not change during transient simulation. Yet, the following pice of code does not work, as during O.P. and transient 0s time vctrl value is fine, but right after 0s time it drops to 0s (treats vctrl as a relay) Code:
How can I get the behavior I need, i.e. have vctrl computed during O.P. and keeping this value throughout transient simulation ? Ari |
Title: Re: Setting voltage in "static" analysis, in keeping it in transient analysis Post by Andrew Beckett on Jan 19th, 2010, 1:20am Because you only have the contribution present during the "static" analysis - i.e. it's only there when the if is active. You need the contribution present all the time - effectively you have a switch branch (I believe) - it's a bit hard to tell without seeing the rest of your model. Regards, Andrew. |
Title: Re: Setting voltage in "static" analysis, in keeping it in transient analysis Post by Ari on Jan 19th, 2010, 5:40am Andrew, Thank you for your reply. I found the following solution: Code:
I'll be happy to know if there are other possible solutions for this. Regards, Ari |
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