The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> Verilog A simulation in spectre
https://designers-guide.org/forum/YaBB.pl?num=1263876595

Message started by amiya on Jan 18^th, 2010, 8:49pm

Title: Verilog A simulation in spectre
Post by amiya on Jan 18^th, 2010, 8:49pm

I have simulated the verilog-A code for and-gate using spectre simulator.
I have stopped the simulator using the statement : kill USR2 <PID> from terminal.
I got the saved state file (*.srf).
When I started the simulation again from the same point (where i have stopped) using the spectre recover statement, it is showing that the simulation is running.
# spectre +lqt 0 tb.scs +recover=tb_recov.srf_10us
But the results are not correct.

The code for AND gate and its test bench, what i have used are given below.

Can You tell how to re-simulate it properly.
------
AND gate code
============
`include "constants.vams"
`include "disciplines.vams"

module andgate (y, a, b, vdd, gnd);
input a, b;
output y;
inout vdd, gnd;
electrical a, b, y, vdd, gnd;

parameter real tr = 10f, tf = 10f, td = 10f;
real y_val, vd, gn, vt;
integer logic1, logic2;

analog begin
vt = 0.5 * V(vdd);
vd = V(vdd);
gn = V(gnd);
logic1 = (V(a) >= vt);
logic2 = (V(b) >= vt);
y_val = (logic1 && logic2) ? vd : gn;
V(y) <+ transition(y_val, td, tr, tf);

end
endmodule

Test bench
=========
V1 (VSS 0) vsource dc=0 type=dc
V0 (VDD 0) vsource dc=1.8 type=dc
I0 (Y VDD B VDD VSS) andgate

Title: Re: Verilog A simulation in spectre
Post by Andrew Beckett on Jan 19^th, 2010, 1:29am

I presume that isn't your entire testbench? No signals are changing, so there wouldn't be much point doing a long transient, and the B input appears to be floating. Also, there's no analysis statements in there, so I can't see what you're actually simulating.

Please give the whole story, not just part of it. And please explain what is "not correct" about the results (maybe a plot to illustrate it?).

It would also be useful to know what version of spectre you're using.

Regards,

Andrew.

Title: Re: Verilog A simulation in spectre
Post by amiya on Jan 19^th, 2010, 2:20am

Hi,
The full test bench goes like below :
------------------------------------------

simulator lang = spectre

//--Netlist--
include "/local_admin_2/amiya/sim/Verilog_A_Lib/tb_andgate//netlist.scs"
//--tran Analysis Setup--
tran tran
+ start=0
+ stop=2e-08
+ outputstart=0
+ step=1e-10
+ errpreset=conservative
+ savetime=[5n 10n 15n 20n]
//---------------------

//--Simulator Setup--
sim_options options
+ reltol=0.001
+ vabstol=1e-06
+ iabstol=1e-12
+ tnom=27
+ scalem=1.0
+ scale=1.0
+ gmin=1e-12
+ rforce=1
+ maxnotes=5
+ maxwarns=5
+ digits=5
+ cols=80
+ pivrel=0.001
+ ckptclock=1800
+ temp=27

dcInfo info what=oppoint where=rawfile
CapInfo info what=captab where=rawfile detail=node
//-------------------

//--Voltages to be Saved--
opt1 options save = all
-----------------------------------------------------------

And the netlist as below :
//---------------------------------------------------------
// Generated for: spectre
// Generated on: Jan 17 14:14:34 2010
// Design library name: Verilog_A_Lib
// Design cell name: tb_andgate

simulator lang=spectre
global 0
ahdl_include "/proj/NMDT_PMDC/PLL/Project/PLL_UMC/Database/schematic/Verilog_A_Lib/andgate/veriloga/veriloga.va"

// Library name: Verilog_A_Lib
// Cell name: tb_andgate

V3 (B 0) vsource type=pulse val0=0.0 val1=1.8 period=2n delay=100f rise=5p \
fall=5p width=995p
V4 (C 0) vsource type=pulse val0=0.0 val1=1.8 period=7n delay=100f \
rise=50p fall=50p width=3.1n
V1 (VSS 0) vsource dc=0 type=dc
V0 (VDD 0) vsource dc=1.8 type=dc
I2 (net14 Y C VDD VSS) andgate
I0 (Y VDD B VDD VSS) andgate

----------------------------------------------

Here, i have one input as VDD and other is a Pulse signal.
I have simulated from 0 to 20ns, where the result Y is as expected, same as input B.
I haved saved the state of simulation at the end of simulation at 20ns. The file name is of extension *.srf
Now I restarted the simulation from 20ns to 40ns, using the same netlist and testbench and the .srf file as recover file using the statement:
spectre +lqt 0 tb.scs +recover=tb.scs.tran.srf_20ns
where tb.scs.tran.srf_20ns is the saved .srf file.
I changed the transient analysis statement as :
//--tran Analysis Setup--
tran tran
+ start=0
+ stop=4e-08
+ outputstart=0
+ step=1e-10
+ errpreset=conservative
+ savetime=[5n 10n 15n 20n 30n 40n]

The simulation output Y from 20ns to 40ns is coming zero, which should follow input B as other input is VDD.

Title: Re: Verilog A simulation in spectre
Post by Andrew Beckett on Jan 19^th, 2010, 6:15am

I just ran your testcase in spectre 7.1.1.275.isr17, and attached is the result I get from the second run (using +recover).

Look OK to me...

As I asked before, what version of spectre are you using? (this will be in the output of spectre).

Regards,

Andrew.

Title: Re: Verilog A simulation in spectre
Post by amiya on Jan 19^th, 2010, 8:28pm

Hi Andrew,

Thank You for your quick reply.

I am using Spectre Version 6.2.0
I will try in the new version.

Regards,

Amiya