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Design >> RF Design >> PLL BW
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Message started by sure on Jan 21^st, 2010, 8:19pm

Title: PLL BW
Post by sure on Jan 21^st, 2010, 8:19pm

hi all,
i am new to this forum as well as pll field.Resently i started reading pll from basic book, regarding loopbandwidth i am hearing that BW<Fref/10 and reason they are explaning above that BW loop will be like more or less sampled domain rather than continuous time domain. But i came to know that there are people who designs PLL with BW equal to Fref/5. I am expecting some basic and understandable reply.

Thanks.

Title: Re: PLL BW
Post by raja.cedt on Jan 21^st, 2010, 10:19pm

hi sure,
i am not that good in that but i will convey whatever i know, according to gadner wn<Wref/(2*G*pi). This he derived from stability point of view ie above this natural frequency pll loop won't behave like continuous time rather it works like sampled data system. so slightly overdamped system means G>1 you can say 2*G*pi is roughly 10, but some designers (as you stated in your post) may use max flat loop behaviour with g=.707 may be they can use Wref/5 >wn.

i have still confusion between wn and BW in presence of zero before UGB. Some people say pll loop BW less than fref/10 but according to gardner discussion wn<fref/10.

Thanks,
Rajasekhar.

Title: Re: PLL BW
Post by vivkr on Jan 22^nd, 2010, 12:51am

The paper by Gardner is a good starting point, but it represents a rule of thumb given the desire to attain a certain level of stability under certain assumptions. However, there are many techniques that have been developed in the meantime. You would need to read up on the literature. I think Razavi's group has done some work there.

A very good paper that covers the topic (you need to be comfortable with state space theory) is:

http://web.engr.oregonstate.edu/~hanumolu/PAPERS/cas1_sep_04.pdf

Regards,

Vivek

Title: Re: PLL BW
Post by Mayank on Jan 27^th, 2010, 5:21am

Hi,
@ sure :
Quote:

i am hearing that BW<Fref/10 and reason they are explaning above that BW loop will be like more or less sampled domain rather than continuous time domain.

At higher Loop Bandwidth, the Loop UGB becomes comparable to comparison frequency. PLL, in actual, has a sampled-time operation, but if BW < Fcomp / 10, you can use continuous time approximation without much loss of accuracy. That's what Gardener suggests too.

Quote:

But i came to know that there are people who designs PLL with BW equal to Fref/5.

Sure you can design PLLs at Fcomp/5 also, if you are willing to take pains to understand and solve PLL in Z-domain. S-domain approximations would no longer be valid.

--
Mayank.