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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> An question about an open-loop comparator https://designers-guide.org/forum/YaBB.pl?num=1264508788 Message started by ray_wang on Jan 26th, 2010, 4:26am |
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Title: An question about an open-loop comparator Post by ray_wang on Jan 26th, 2010, 4:26am Dear all, I use an differential-to-single open-loop amplifer with an inverter chain as a comparator. The reason why I don't use a dynamic comparator is that this comparator needs to work continuously. However, I found that even if the input is changing slowly (you can see from the pic, with the inverter chain delay being at most 500ps), there would be some "overshoot". I mean, vinn must be smaller than vinp by 21mV for the output to change. Moreover, this 21mV is process-dependant, which introduces significant error in my design. I want to reduce that 21mV to less than 2mV. Is there anybody familiar with this kind of comparator helping me? I also want to know if there is some discussion/paper/thesis on this comparator or some better structure. Your comment is appeciated. |
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Title: Re: An question about an open-loop comparator Post by Mayank on Jan 27th, 2010, 3:40am Hi, Seems like systematic offset b/w load transistors of the diff-2-single ended opamp. Did you check that ? Also, why not use a cross coupled Level-Shifter kinda topology instead of a D2SE opamp. here inverter chain has an inherent delay of 500ps. Cross-Coupled would be faster & you will get differential output signals directly. -- Mayank. |
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Title: Re: An question about an open-loop comparator Post by boe on Jan 28th, 2010, 10:25am ray_wang, I expect that some of your "error" is simply comparator delay. BOE |
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Title: Re: An question about an open-loop comparator Post by loose-electron on Jan 28th, 2010, 5:26pm Very strange architecture. Why dont you consider some more conventional approaches? |
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Title: Re: An question about an open-loop comparator Post by ray_wang on Jan 31st, 2010, 2:42am Hi, Mayank This comparator is used in an feedback loop to form an relaxation oscillator and I use the inverter chain here just to avoid metastability. And I don't think its contribution to the overall delay is significant. Here I only want to increase the speed of the open-loop opamp. I searched "cross coupled Level-Shifter", but I did not get what I desired. Could you provide more details? After posting, I randomly swept the transistors' size and got a much better result. And I found that the result is even worse if I use PMOS input diff-pair. But to be frank, I still don't know exactly the mechanism about that "overshooting". :-/ To BOE, You are right, but I believe there is systematic delay for the comparator, not just common intrinsic delay, since 2ns is too large for 0.18um devices. To loose-electron, I don't know what "conventional approaches" are, can you provide me with information on continously-working fast comparator? Thank you for your comment. :) |
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Title: Re: An question about an open-loop comparator Post by loose-electron on Jan 31st, 2010, 9:47am ray_wang wrote on Jan 31st, 2010, 2:42am:
Take a look at this - http://ece-classweb.ucsd.edu/winter10/ece264c/Comparator_Supplemental.pdf |
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Title: Re: An question about an open-loop comparator Post by ray_wang on Feb 5th, 2010, 8:27am Thank you for your help! loose-electron wrote on Jan 31st, 2010, 9:47am:
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Title: Re: An question about an open-loop comparator Post by boe on Feb 9th, 2010, 12:59am ray_wang wrote on Jan 31st, 2010, 2:42am:
BTW: I agree with loose-electron as well. BOE |
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