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Design >> RF Design >> Very curious about optimum impedance from load-pull in PA designs
https://designers-guide.org/forum/YaBB.pl?num=1264582305

Message started by DoYouLinux on Jan 27^th, 2010, 12:51am

Title: Very curious about optimum impedance from load-pull in PA designs
Post by DoYouLinux on Jan 27^th, 2010, 12:51am

Hi all,

I have some questions to ask about optimum load impedance in power amplifiers designs.

As can be seen from the attached figure, in order to obtain maximum output power, we need to use load-pull simulation to find an optimum load impedance (Zopt). Then, we design an impedance transformation network to transform the 50-ohm load to be Zopt.

With this matching network, the transistor will see Zopt at its drain, and will deliver maximum power to the 50-ohm load (assuming lossless matching network).

What I am wondering is that, what is the impedance seen by the 50-ohm load (Zx in the figure) ? I think that we cannot know the value of this impedance during the design process of the matching network, because we don't do conjugate matching at the output.

So, if Zx is very different from 50 ohm, there will be high reflection at the junction between the 50-ohm load and the matching network.

In the design process, how could we deal with Zx ?

I found that, if S22 is too high (order of -3 dB), K factor will be lower than 1.

Thank you for your reply in advance,

DYL

Title: Re: Very curious about optimum impedance from load-pull in PA designs
Post by vivarf on Jan 27^th, 2010, 3:15am

Hi,

To the best of my knowledge, the impedance seen by Zload is Z*load, which is 50 Ohm in this case. Start from Zload' side, the matching network transfer Zload to Zopt, so the power amplifier will deliver maximum power to Zopt then to the Zload through matching network
I am also interested in this area, and I would love to be corrected if I was wrong. Thanks

Title: Re: Very curious about optimum impedance from load-pull in PA designs
Post by DoYouLinux on Jan 27^th, 2010, 3:59am

Hi vivarf,

Thanks for feedback. Yes, the role of the output mathcing network of the PA is to transform Zload = 50 ohm to Zopt at the drain of the transistor.

However, how could we make the matching network to match the 50 ohm load at the same time ??? Load pull simulations will not give any idea about this and hence Zx is left unknown. So, when Zx is far from 50ohm, S22 becomes larger and we will have a problem with stability.

My main question is how could we deal with Zx such that we can minimize S22 at the same time we maximize Pout ?????

Best regards,

DYL

Title: Re: Very curious about optimum impedance from load-pull in PA designs
Post by pancho_hideboo on Jan 27^th, 2010, 4:14am

First of all, how do you measure or define Zx ?

With input to gate, that is, with output power ?
Without input to gate, that is, without no output power ?

See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1246435268
http://www.designers-guide.org/Forum/YaBB.pl?num=1214811603

Title: Re: Very curious about optimum impedance from load-pull in PA designs
Post by DoYouLinux on Jan 27^th, 2010, 4:56pm

Hi Pancho,

Thank you for feedback. At the input, I terminated the gate with an input matching network and the PORT element. Then I set PORT input and PORT output (1 & 2) to DC to do small-signal S parameter simulation. From the results, I could notice that, sometimes S22 were very good, like I am conjugately matching the 50 ohm load (from PORT2), but this was not my intention in the design process. If this happened, K will be greater than 1. However, sometimes (I mean in some designs when I changed Zopt), S22 became worse (-3 dB) and K < 1. Again, it seems that the impedance seen by the 50-ohm load (Zx in the figure) is very different from 50 ohm, which I don't know how to control it.

What I know is how to get Zopt from load pull simulation, then create an impedance transformation network to transform 50-ohm load to be Zopt. For Zx, I have no idea how to deal with it.

Thank you for feedback again,

DYL

Title: Re: Very curious about optimum impedance from load-pull in PA designs
Post by pancho_hideboo on Jan 27^th, 2010, 7:17pm

DoYouLinux wrote on Jan 27^th, 2010, 4:56pm:

At the input, I terminated the gate with an input matching network and the PORT element.
Then I set PORT input and PORT output (1 & 2) to DC to do small-signal S parameter simulation.

Generally such static state small signal S22 doesn't have much meanings for PA.

DoYouLinux wrote on Jan 27^th, 2010, 4:56pm:

However, sometimes (I mean in some designs when I changed Zopt),
S22 became worse (-3 dB) and K < 1.

If your concerns are static state small signal S22 and K which don't have much meanings for PA, K can be improved by modifying input matching network in front of MOSFET gate.

You should study a concept of "Conditionally Stable".
http://www.designers-guide.org/Forum/YaBB.pl?num=1218635777/5#5

As another option, K could be improved by neutralization.

Quote:

Again, it seems that the impedance seen by the 50-ohm load (Zx in the figure) is very different from 50 ohm, which I don't know how to control it.

Again your static state small signal Zx doesn't have much meanings for PA.
Also again see the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1246435268
http://www.designers-guide.org/Forum/YaBB.pl?num=1214811603

Title: Re: Very curious about optimum impedance from load-pull in PA designs
Post by DoYouLinux on Jan 28^th, 2010, 12:48am

Hi Pancho_Hideebo,

Thank you very much for the information. I will study about it. You are a very nice guy.

DYL