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Design >> Mixed-Signal Design >> Mixed Signal Noise & Simulation vs. Silicon
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Message started by loose-electron on Jan 27^th, 2010, 12:33pm

Title: Mixed Signal Noise & Simulation vs. Silicon
Post by loose-electron on Jan 27^th, 2010, 12:33pm

OK Everyone -

I got these two presentations posted up on my UCSD class web site, because the students are going to be hearing about this stuff from me near the end of the quarter.

At the bottom of the page (link below) You can download the presentations (.pdf):

http://ece-classweb.ucsd.edu/winter10/ece264c/

Links are at the bottom of the page.

One of these is
"everything you want to know about interference noise and how to minimize"
And the other is:
"all the other problems you can encounter when fabricating a chip, and the simulations and the chip don't do the same thing"

Enjoy! (copyright me ;) - no stealing!)

Feel free to post comments on the content here. If you want to be taught the material in here, I do seminars on the subject as well.

regards,
Jerry

Title: Re: Mixed Signal Noise & Simulation vs. Silicon
Post by loose-electron on Feb 1^st, 2010, 6:03pm

no comments eh? Is that a good thing or a bad thing?

Title: Re: Mixed Signal Noise & Simulation vs. Silicon
Post by Mayank on Feb 1^st, 2010, 9:37pm

Hi Jerry,
Cool to know you are taking up the course on Data Converters at UCSD....
[...I had an admit from UCSD...Had it not been for the financial aid :(, i might have been there studying under you....]
But anyways, since right now i am not, i guess i can comment/compliment 8-)

The Noise in Mixed Signals IC's lecture is really a very comprehensive one. It kinda includes most of the points. I will read it attentively when i have some more time.

The one on Simulation vs. Silicon is a bit more of a superficial knowledge of everything without a deep investigation of a particular topic. I guess you gotta be the Jack of all Trades sometimes :P The topic you are addressing is itself comprised of statistics mostly. It's all about yields and failures. You could include some statistics.
Also, where you talk about Separation of Digital and Analog Domain, you could include some fundas of STAR routing etc to prevent direct noise coupling from digital side. Also, you could include some topic on how to create measurement setups for final fab'ed chip and what care should be taken in those measurement setups.

Nice lectures overall. Pleasure reading [ esp. the Nosie in MS chips one]
--
Mayank

Title: Re: Mixed Signal Noise & Simulation vs. Silicon
Post by solidstate on Feb 2^nd, 2010, 1:05pm

Thanks, interesting stuff! It reads like condensed experience ;)

Title: Re: Mixed Signal Noise & Simulation vs. Silicon
Post by loose-electron on Feb 2^nd, 2010, 4:45pm

"condensed experience" is an apt description....

Title: Re: Mixed Signal Noise & Simulation vs. Silicon
Post by Berti on Feb 3^rd, 2010, 12:03am

Hi Jerry,

Nice lecture notes!

Recently I was confronted with a bad PDK. I found it a very tedious task to figure out which effects are not included in the transistors models. While some deficiencies like missing STI-stress models have been easy to find, you never know whether the model has been properly characteristic or not ... unless you start measuring you own test-structures.

How do I know whether the model is correct or not? Are they some 'easy' checks without spending weeks for studying the provided BSIM model?

Thanks for sharing your experience.
Cheers

Title: Re: Mixed Signal Noise & Simulation vs. Silicon
Post by loose-electron on Feb 3^rd, 2010, 2:33pm

Oh yeah - you need to read this:
http://effectiveelectrons.com/modeling.htm

and this for the do it yourself version:

http://chipdesignmag.com/display.php?articleId=438&issueId=16

I wrote that for Chip Design about 4 years back

Berti wrote on Feb 3^rd, 2010, 12:03am: