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Simulators >> RF Simulators >> PLL Simulation with white noise
https://designers-guide.org/forum/YaBB.pl?num=1264756549

Message started by Mayank on Jan 29^th, 2010, 1:15am

Title: PLL Simulation with white noise
Post by Mayank on Jan 29^th, 2010, 1:15am

Hi,
I am trying to simulate a PLL with transient noise enabled...
Also i am placing a 10mV white noise source on VDD.....through a verilogA model using $rdit_normal() function.
I have modelled supply inductance + interconnect resistance through a small, finite-Q inductance.

White Noise source works properly.....But the ckt simulation time increased a LOT !!! around 1ps / sec.
Can't simulate this way......Are there any better methods to simulate transient noise with a noisy supply ???

--regards,
Mayank.

Title: Re: PLL Simulation with white noise
Post by sheldon on Jan 29^th, 2010, 3:06am

Mayank,

Have you resistor and a vcvs?

Sheldon