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Simulators >> Circuit Simulators >> Probe inside a verilog-A module
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Message started by ywguo on Feb 4^th, 2010, 8:46pm

Title: Probe inside a verilog-A module
Post by ywguo on Feb 4^th, 2010, 8:46pm

Hi Guys,

How do I probe inside a verilog-A module? As well known, signals and variable can be defined in side a verilog-A module. I am simulating a behavioral model written in verilog-A. I want to probe inside the verilog-A module to debug.

The simulation tool is spectre. I use ADE as the GUI interface.

Best Regards,
Yawei

Title: Re: Probe inside a verilog-A module
Post by Andrew Beckett on Feb 5^th, 2010, 2:03am

Hi Yawei,

In the Outputs->Save All form, set the "saveahdlvars" setting to "all".

Then you'll be able to see internal variables in the results browser.

Regards,

Andrew.

Title: Re: Probe inside a verilog-A module
Post by ywguo on Feb 6^th, 2010, 8:11pm

Thank you, Andrew.