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Design >> Mixed-Signal Design >> MOSFET Zero Bias Gate Capacitance
https://designers-guide.org/forum/YaBB.pl?num=1265671457

Message started by Mooraka on Feb 8^th, 2010, 3:24pm

Title: MOSFET Zero Bias Gate Capacitance
Post by Mooraka on Feb 8^th, 2010, 3:24pm

Hi,
Can any body give me an example digital/analog ckt where the zero bias (Vgs=0) gate capacitance (Cgg) is critical?.

I see some of the digital blocks like ring oscillators and standard cells where load cap changes matters, but I think inversion capacitance plays dominant role there.

Thanks

Title: Re: MOSFET Zero Bias Gate Capacitance
Post by Berti on Feb 9^th, 2010, 1:00am

For a MOS transistor in inversion Cgg goes towards zero for Vgs=0 ... so I don't understand your question.

Cheers

Title: Re: MOSFET Zero Bias Gate Capacitance
Post by Mooraka on Feb 9^th, 2010, 7:14am

When Vgs=0, the device is off and the gate capacitance is a combination of oxide cap in series with depletion cap and overlap cap. This value is low (approx half) compared to gate capacitance at Vgs=Vcc, which is inversion capacitance (approx equal to oxide cap).

My question is, is there any circuit that heavily depends on FET zero bias capacitance?

Thanks