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Design Languages >> Verilog-AMS >> counter
https://designers-guide.org/forum/YaBB.pl?num=1266065810

Message started by manikandan on Feb 13^th, 2010, 4:56am

Title: counter
Post by manikandan on Feb 13^th, 2010, 4:56am

hi..

i want to divide the input frequency by 40..am using a 6 bit counter that resets at 101000(40)..i.e when d3 and d5 are 1 then counter nust reset..
am new to verilog a and cadence..i didnt get the output wave which should actually remain high for 40 input clocks..help pls..

include "constants.vams"
include "disciplines.vams"

module bitcounter(clkout,clk,reset);
output clkout;
electrical clkout;M
input clk;
electrical clk;
input reset;
electrical reset;

parameter real vlogic_high=3.3;
parameter real vlogic_low=0;
parameter real vtrans_clk=1.65;
parameter real vtrans_reset=1.65;
parameter real tdel=60p;
parameter real trise=100p;
parameter real tfall=100p;

integer reset_flag;
integer count;
integer d[0:5];
integer i;

analog begin

@ (cross(v(clk)-vtrans_clk, +1)) begin
if(v(reset) < vtrans_reset) begin
if (d[3]&&d[5]) begin // is this correct?
reset_flag = 1;
count=0;
end
end

else
reset_flag=0;

for(i=0;i<=5;i=i+1) begin
count=count+1;
end
end

v(clkout) <+ transition (vlogic_high*d[5]*d[3]*!reset_flag, tdel, trise, tfall);
end
endmodule

//is this a correct approach?

Title: Re: counter
Post by pancho_hideboo on Feb 14^th, 2010, 9:56am

manikandan wrote on Feb 13^th, 2010, 4:56am:

am new to verilog a and cadence..

What do you mean by "cadence" ?

The followings are general notes for you.

- Always describe vendor's name which you use as tool or simulator.
- Don't do multiple posts which are same content.
- Don't request source code or behavioral model without any efforts.
- There are many simulators which have analyses called as PSS, PAC and Pnoise.
- Describe in detail with using correct terminologies.
- Warnigns are different from Errors.
- ADS is not name of simulator.
- There is no tool which name is Cadence.
- Don't use Direct Plot of Cadence ADE blindly without knowing definition.
- All gains in Direct Plot of Cadence ADE are "right", "true" and "practical" voltage gain.
- Don't mix up Simulation with Post Processing. They are completely different phase.
- MATLAB are different from Simulink.
- Learn measurements using actual instruments. Not "EDA Tool Play

manikandan wrote on Feb 13^th, 2010, 4:56am:

i didnt get the output wave which should actually remain high for 40 input clocks..help pls..

I can't understand what you mean by "actually remain high for 40 input clocks".
If output wave is high during 40 input clocks, divide ratio is 80 not 40.

And before arguing output wave, there are syntax errors and many incompletenessed in your Verilog-A code.
Do you truely run this Verilog-A code.

manikandan wrote on Feb 13^th, 2010, 4:56am:

module bitcounter(clkout,clk,reset);
output clkout;
electrical clkout;M
input clk;
electrical clk;
input reset;
electrical reset;

parameter real vlogic_high=3.3;
parameter real vlogic_low=0;
parameter real vtrans_clk=1.65;
parameter real vtrans_reset=1.65;
parameter real tdel=60p;
parameter real trise=100p;
parameter real tfall=100p;

integer reset_flag;
integer count;
integer d[0:5];
integer i;

analog begin

@ (cross(v(clk)-vtrans_clk, +1)) begin
if(v(reset) < vtrans_reset) begin
if (d[3]&&d[5]) begin // is this correct?
reset_flag = 1;
count=0;
end
end

else
reset_flag=0;

for(i=0;i<=5;i=i+1) begin
count=count+1;
end
end

v(clkout) <+ transition (vlogic_high*d[5]*d[3]*!reset_flag, tdel, trise, tfall);
end
endmodule

//is this a correct approach?

Do you think so?
First, there is no definition for d[3] and d[5]. How do you define "d[0:5]" ?

Remake verilog-A code after studying the following.
http://www.designers-guide.org/VerilogAMS/functional-blocks/freq-divider/freq-divider.va

Title: Re: counter
Post by Geoffrey_Coram on Feb 15^th, 2010, 11:32am

I guess Pancho didn't see the declaration
integer d[0:5];

but I don't see any assignment to d, only using the values.

Title: Re: counter
Post by pancho_hideboo on Feb 15^th, 2010, 2:46pm

Geoffrey_Coram wrote on Feb 15^th, 2010, 11:32am:

I guess Pancho didn't see the declaration
integer d[0:5];
but I don't see any assignment to d, only using the values.

I mean this. And I know there is "integer d[0:5];".

Title: Re: counter
Post by Marq Kole on Mar 4^th, 2010, 6:21am

I guess that d[3] && d[5] tries to check whether the bits 3 and 5 of integer d are set. That is not the way to code this in Verilog-A. This is not digital hardware, not even RTL. The simple check should probably be:

if (count >= 40)

When starting from scratch with a model it is best to write the model in plain code, and not try to do some optimizations. Once the model works you can still apply these optimizations, the first target should be a working model. This applies to any model and any language!

Cheers,
Marq

Title: Re: counter
Post by pancho_hideboo on Mar 4^th, 2010, 6:33am

Marq Kole wrote on Mar 4^th, 2010, 6:21am:

I guess that d[3] && d[5] tries to check whether the bits 3 and 5 of integer d are set.

Problem is there is no assignment for d[5:0] in code.
Even if this code is Verilog-D or Verilog-AMS, there is no counting description for d[5:0].

To make this code workable as Verilog-A, count number should be mapped to d[5:0] for example.

However see the following. He abandoned to use d[5:0].
http://www.designers-guide.org/Forum/YaBB.pl?num=1266353533/2#2