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Design >> Analog Design >> Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
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Message started by Manas on Feb 15^th, 2010, 2:51am

Title: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 15^th, 2010, 2:51am

Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C feed back circuit is used.
Please see the attached file for the Diagram.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by raja.cedt on Feb 15^th, 2010, 4:05am

hi mans,
due to op amp input parasitic capacitance, if you use only resistive divider you don't see proper step response due to additional pole at the op amp input. So probably they are ding pole zero compensation with the help of this passive network.

Thanks,
rajasekhar.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 15^th, 2010, 11:24pm

Hi Rajsekhar,
So ur telling if we use Resistive feedback the loop-gain Phase is getting degraded due to the i/p Cap of OPAMP and hence the stability and BW. If this is the problem then one can use ONLY Capacitor feed-back and get out of the jail. This can also give the DC -ve Feed-back.Why bother about both RESISTOR and CAPACITOR

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Berti on Feb 16^th, 2010, 12:31am

Rajasekhar, can you please elaborate on your answer. Why should the input capacitance of the amplifier degrade settling?

Manas, for which frequencies is this testing configuration used?
I think that the capacitors provide the actual (low) impedance feedback while the resistors are only used to define the DC operating point. Would you use only resistors, the amplifier would be resistively loaded, while using only capacitors, the DC operating point at the input of the amplifier will not be defined.

Regards

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 16^th, 2010, 12:59am

Berti wrote on Feb 16^th, 2010, 12:31am:

Berti,
The testing configuration is used for to Characterize an OPAMP (to find UGB,Slew rate,IM3 and so on). Also these type of configuration is very common. Any paper you open you will find this type of set-up for testing the Chip(OPAMP).
I have some doubts on your Comments-->
1)Why one needs low impedance feed-back.What does it actually
mean?
2)Why you are saying Cap divider can't give DC biasing point. Two capacitors can divide the DC voltage like Resistive Divider. Isn't It :)

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 16^th, 2010, 2:16am

Manas wrote on Feb 16^th, 2010, 12:59am:

2)Why you are saying Cap divider can't give DC biasing point.
Two capacitors can divide the DC voltage like Resistive Divider. Isn't It

Consider a case where an inverted input node is charged.
What voltage do you think it results in ?

If feedback networks are composed of only capacitor,
- It is difficult to fix DC bias points properly.
It could results in extreme bias points, e.g. all devices are saturated or cut off.
This is very true for CMOS OP Amp.
- No feedback effect at DC and low frequency. It could cause unstability.

If feedback networks are composed of only resistor,
- It could be unstable for high frequency.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 16^th, 2010, 3:27am

pancho_hideboo wrote on Feb 16^th, 2010, 2:16am:

Manas wrote on Feb 16^th, 2010, 12:59am:

2)Why you are saying Cap divider can't give DC biasing point.
Two capacitors can divide the DC voltage like Resistive Divider. Isn't It

Consider a case where an inverted input node is charged.
What voltage do you think it results in ?

Thanks A lot,
Just to tell about your question above-->
Suppose the cap (Cin) from inverting node to Gnd(no ac signal) has +ve Charge, then the OPAMP o/p voltage will fall this in turn sucks charge from the inverting node through the F/B CAP(Cf) and the -node will be reverted back to voltage at the + node of the OPAMP as -ve DC feed-back still exists in case of CAP divider.

Just one-thing to mention that Cf/Cin+Cf is equivalent to Rin/Rf+Rin as both are frequency independent. :)

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 16^th, 2010, 3:31am

Manas wrote on Feb 16^th, 2010, 3:27am:

Suppose the cap (Cin) from inverting node to Gnd(no ac signal) has +ve Charge,
then the OPAMP o/p voltage will fall this in turn sucks charge from the inverting node
through the F/B CAP(Cf) and the -node will be reverted back to voltage at the + node of the OPAMP
as -ve DC feed-back still exists in case of CAP divider.

I can't understand what you want to claim.

Both charge(Qx) and capacitance(Cx) of inverted node are unknown.
And Qx might be negative.

Manas wrote on Feb 16^th, 2010, 3:27am:

Just one-thing to mention that Cf/Cin+Cf is equivalent to Rin/Rf+Rin as both are frequency independent.

They are different regarding DC characteristics although they are same regarding AC characteristcs.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by raja.cedt on Feb 16^th, 2010, 6:57am

hi barthi,
i feel due to op amp input cap there will be one extra pole which may impact Ts...what's the issue in this

thanks
Rajasekhar.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Berti on Feb 16^th, 2010, 11:44pm

Rajasekhar,

Quote:

i feel due to op amp input cap there will be one extra pole which may impact Ts...what's the issue in this

This 'feeling' can be resolved by simple hand-calculations. However, since the input cap of the opamp is basically in parallel to the input capacitance I don't see how an additional pole should be created.

Manas, I was wondering about the frequencies of interest since already for reasonably high frequencies (>1MHz) the impedance will be dominated by the capacitor (for the values given in your figure). The resistors therefore only serves to define the DC operating point. - as Pancho explained quite well.

Cheers

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 17^th, 2010, 9:52pm

link=1266231079/0#6 date=1266319631]Suppose the cap (Cin) from inverting node to Gnd(no ac signal) has +ve Charge,
then the OPAMP o/p voltage will fall this in turn sucks charge from the inverting node
through the F/B CAP(Cf) and the -node will be reverted back to voltage at the + node of the OPAMP
as -ve DC feed-back still exists in case of CAP divider.[/quote]I can't understand what you want to claim.

IN RESPONSE TO ABOVE MENTIONED Q-->
I MEAN TO SAY THAT ANY SPURIOUS CHARGE CAN BE REMOVED BECAUSE OF OPAMP ACTION AND IN THE STEADY STATE IT WILL BE SAME AS IF YOU DON'T HAVE ANY CHARGE IN THE CAP.

Both charge(Qx) and capacitance(Cx) of inverted node are unknown.
And Qx might be negative.

IN RESPONSE TO ABOVE Qn-->
THE VOLTAGE AT THE ASKED NODE IS --> = Vdd * [C2/(C1+CX+C2)]. AS CHARGE REDISTRIBUTION HAPPENS.
PLEASE NOTE THAT IF C1>>CX (AS MENTIONED IN MY DIAGRAM 2.5pf), THE EFFECT OF Cx CAN BE NEGLECTED AND ONE CAN GET THE DESIRED VOLTAGE DIVISION.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 17^th, 2010, 9:58pm

raja.cedt wrote on Feb 16^th, 2010, 6:57am:

hi barthi,
i feel due to op amp input cap there will be one extra pole which may impact Ts...what's the issue in this

thanks
Rajasekhar.

Rajasekhar
Why you r telling there will be pole ? if there is no resistor feed-back ??
Don't u think one can give DC -ve feed-back with CAP only ??

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 17^th, 2010, 9:58pm

raja.cedt wrote on Feb 16^th, 2010, 6:57am:

hi barthi,
i feel due to op amp input cap there will be one extra pole which may impact Ts...what's the issue in this

thanks
Rajasekhar.

Rajasekhar
Why you r telling there will be pole ? if there is no resistor feed-back ??
Don't u think one can give DC -ve feed-back with CAP only ??

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 18^th, 2010, 12:48am

Manas wrote on Feb 17^th, 2010, 9:52pm:

I MEAN TO SAY THAT ANY SPURIOUS CHARGE CAN BE REMOVED BECAUSE OF OPAMP ACTION
AND IN THE STEADY STATE IT WILL BE SAME AS IF YOU DON'T HAVE ANY CHARGE IN THE CAP.

Not correct.

First, Vx is a floating node. So Qx can not be removed.
Second, it could result in stagnated bias points. So OP Amp can't work correctly.

Manas wrote on Feb 17^th, 2010, 9:52pm:

THE VOLTAGE AT THE ASKED NODE IS --> = Vdd * [C2/(C1+CX+C2)].
AS CHARGE REDISTRIBUTION HAPPENS.
PLEASE NOTE THAT IF C1>>CX (AS MENTIONED IN MY DIAGRAM 2.5pf),
THE EFFECT OF Cx CAN BE NEGLECTED AND ONE CAN GET THE DESIRED VOLTAGE DIVISION.

Not correct.

C1, C2 and Cx share Qx in initial state.
Qx is not charged in only small Cx.
So after restribution of charge, I can't expect Vx correctly.

If feedback networks are composed of only capacitor,
- It is difficult to fix DC bias points properly.
It could results in extreme bias points, e.g. all devices are saturated or cut off.
This is very true for CMOS OP Amp.
- No feedback effect at DC and low frequency. It could cause unstability.

If feedback networks are composed of only resistor,
- It could be unstable for high frequency.

Manas wrote on Feb 17^th, 2010, 9:58pm:

Don't u think one can give DC -ve feed-back with CAP only ??

Again, there is no feedback for DC if feedback network is composed of only capacitor.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 18^th, 2010, 12:53am

The following is duplicated. Please delete this post.

http://www.designers-guide.org/Forum/YaBB.pl?num=1266231079/12#12

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 18^th, 2010, 4:06am

pancho_hideboo wrote on Feb 18^th, 2010, 12:48am:

Manas wrote on Feb 17^th, 2010, 9:52pm:

I MEAN TO SAY THAT ANY SPURIOUS CHARGE CAN BE REMOVED BECAUSE OF OPAMP ACTION
AND IN THE STEADY STATE IT WILL BE SAME AS IF YOU DON'T HAVE ANY CHARGE IN THE CAP.

Not correct.

First, Vx is a floating node. So Qx can not be removed.
Second, it could result in stagnated bias points. So OP Amp can't work correctly.

[quote author=MANASKUMAR link=1266231079/0#10 date=1266472320]THE VOLTAGE AT THE ASKED NODE IS --> = Vdd * [C2/(C1+CX+C2)].
AS CHARGE REDISTRIBUTION HAPPENS.
PLEASE NOTE THAT IF C1>>CX (AS MENTIONED IN MY DIAGRAM 2.5pf),
THE EFFECT OF Cx CAN BE NEGLECTED AND ONE CAN GET THE DESIRED VOLTAGE DIVISION.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 18^th, 2010, 4:09am

Manas wrote on Feb 18^th, 2010, 4:06am:

I AM WRONG. AS IT IS A FLOATING NODE, THE Qx CHARGE CAN'T BE REMOVED.
HENCE THAT POINT CAN'T HAVE DESIRED VOLTAGE DUE TO OPAMP ACTION.

If you would like to insist on feedback networks composed of only capacitor, you should implement some startup circuits, e.g. reset circuit.

But unstability issue never can be resolved even if you implement startup circuit with feedback networks compopsed of only capacitor.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 18^th, 2010, 11:06pm

But unstability issue never can be resolved even if you implement
startup circuit with feedback networks compopsed of only capacitor.
[/quote]

Thanks A Lot !!
Can u provide any example or cases where the above mentioned issue has happened or the designers have faced the problems??
You may point to any reference paper or material..

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 19^th, 2010, 1:37am

Manas wrote on Feb 18^th, 2010, 11:06pm:

Can u provide any example or cases where the above mentioned issue has happened or the designers have faced the problems??

Assume opened input(left terminal of C1) with feedback networks composed of only capacitor C2.

Here there is no feedback effect around DC and low frequency. This is almost open loop high gain OP Amp alone.
So it could cause unstability around low frequency due to contiunous time operation.

On the other hand, capacitor only feedback networks are used in switched capacitor amplifier.
The reason why it could not be unstable is due to its discrete time operation.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 22^nd, 2010, 1:51am

This is Just for Completion of the Discussion of the POST. I have attached the desired files

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 22^nd, 2010, 1:52am

Manas wrote on Feb 22^nd, 2010, 1:51am:

This is Just for Completion of the Discussion of the POST. I have attached the desired files

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 22^nd, 2010, 1:52am

Manas wrote on Feb 22^nd, 2010, 1:52am:

Manas wrote on Feb 22^nd, 2010, 1:51am:

This is Just for Completion of the Discussion of the POST. I have attached the desired files

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 22^nd, 2010, 2:03am

For only resistor feedback networks, you should consider instability due to load capacitance rather than input capacitance.

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by Manas on Feb 22^nd, 2010, 2:39am

pancho_hideboo wrote on Feb 22^nd, 2010, 2:03am:

For only resistor feedback networks, you should consider instability due to load capacitance rather than input capacitance.

Of-Course due to Load Capacitance the Phase of the Stand-Alone OPAMP phase degrades even if there is resistive feed-back or not ( is a lose statement. It may improves the stability).

If I break the loop at the o/p node of the OPAMP and apply a Vtest at the break point then the Resistors and the i/p cap forms a Low-pass filter and adds a effective pole in the LOOP-gain as the Feed-back ressistors are kept quite high for not reducing (loading) OPMAP o/p resistance.

I wonder how due to the resistive feed-back and the load capacitance the pole is added in the Loop-gain. Putting the my doubt i other way--> How resistive feed-back degrades the pole caused by the load Capacitor

Title: Re: Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe
Post by pancho_hideboo on Feb 22^nd, 2010, 2:44am

Manas wrote on Feb 22^nd, 2010, 2:39am:

Putting the my doubt i other way-->
How resistive feed-back degrades the pole caused by the load Capacitor

Simply consider output resistance of OP Amp.
Then consider resistance only feedback with it and load capacitance.

It could result in positive feedback.