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Design Languages >> Verilog-AMS >> programmable divider
https://designers-guide.org/forum/YaBB.pl?num=1266245690

Message started by manikandan on Feb 15^th, 2010, 6:54am

Title: programmable divider
Post by manikandan on Feb 15^th, 2010, 6:54am

hi,
i need verilog-a code for programmable divider which will be used in a PLL..the VCO output frequency is 400Mhz and 420 Mhz..PLL input reference is 10Mhz..thus ill need division ratios of 40 and 42..i have two counters with those division ratios..but how do i program it?

Title: Re: programmable divider
Post by pancho_hideboo on Feb 15^th, 2010, 7:13am

This post is substantially same content as your following post.
http://www.designers-guide.org/Forum/YaBB.pl?num=1266065810

http://www.designers-guide.org/Forum/YaBB.pl?num=1260351750/5#5

The followings are general notes for you.

- Always describe vendor's name which you use as tool or simulator.
- Don't do multiple posts which are same content.
- Don't request source code or behavioral model without any efforts.
- There are many simulators which have analyses called as PSS, PAC and Pnoise.
- Describe in detail with using correct terminologies.
- Warnigns are different from Errors.
- ADS is not name of simulator.
- There is no tool which name is Cadence.
- Don't use Direct Plot of Cadence ADE blindly without knowing definition.
- All gains in Direct Plot of Cadence ADE are "right", "true" and "practical" voltage gain.
- Don't mix up Simulation with Post Processing. They are completely different phase.
- MATLAB are different from Simulink.
- Learn measurements using actual instruments. Not "EDA Tool Play