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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> help with syntax https://designers-guide.org/forum/YaBB.pl?num=1266353533 Message started by manikandan on Feb 16th, 2010, 12:52pm |
Title: help with syntax Post by manikandan on Feb 16th, 2010, 12:52pm hi how can this logic be implemented in verilog A.. if(voltage input high ) condition 1 elseif(voltage input low) condition 2 |
Title: Re: help with syntax Post by Geoffrey_Coram on Feb 16th, 2010, 2:46pm module mymod(in); input in; electrical in; parameter real vhigh = 0.7; parameter real vlow = 0.3; analog begin if (V(in) > vhigh) statement1; else if (V(in) < vlow) statement2; end endmodule |
Title: Re: help with syntax Post by manikandan on Feb 17th, 2010, 2:00am i got this error..pls help me fix it..according to voltage in i want the division ratio to change.. `include "constants.vams" `include "disciplines.vams" module freqdividerduty(out, vcoin, in); output out; voltage out; // output input vcoin; voltage vcoin; // input (edge triggered) input in; voltage in; parameter real vh=+3.3; // output voltage in high state parameter real vl=0; // output voltage in low state parameter real vth=(vh+vl)/2; // threshold voltage at input parameter integer ratioone=40 from [40:inf); // divide ratio parameter integer ratiotwo=41 from [40:inf); // divide ratio parameter real tt=1n from (0:inf); // transition time of output signal parameter real td=0 from [0:inf); // average delay from input to output integer count,x,y; analog begin @(cross(V(vcoin) - vth, +1)) begin count = count + 1; // count input transitions if (count >= y) count = 0; end if (count <= (y/2)) begin x = 1; end else begin x = 0; end end if (V(in) = vh) y = ratioone; elseif (V(in) = vl) y = ratiotwo; else y = 0; V(out) <+ transition(x ? vh : vl, td, tt); end endmodule "/proj/ek/vlsi4/common_libs/project_main_shared/freqdividerduty/veriloga/veriloga.va", line 22: Warning: (Archaic Syntax) Does not comply with the Accellera Verilog-AMS 2.0 Standard and beyond. To comply with the current standard, assign a value to `y'. A variable that is never assigned a value is considered a digital variable in Verilog-AMS and is therefore not pure Verilog-A. Error found by spectre during SpectreHDL compile. "/proj/ek/vlsi4/common_libs/project_main_shared/freqdividerduty/veriloga/veriloga.va", line 39: "if<<--? (V(in) = vh)" "/proj/ek/vlsi4/common_libs/project_main_shared/freqdividerduty/veriloga/veriloga.va", line 39: Error: syntax error Maximum allowable errors exceeded. Exiting AHDL compilation.... |
Title: Re: help with syntax Post by Andrew Beckett on Feb 17th, 2010, 3:02am If you actually indented your code (consistently), it would make it much easier for you to identify the mistake which is causing this (and then uncover the subsequent errors). First thing, look around the line where the problem occurs: Code:
You have two successive end statements. The second of these is closing the begin associated with the analog statement. So it shouldn't be there. Having fixed that, you have some other issues Code:
You've used an assignment rather than an equality check (==) in this statement. That said, using an equality check is not a good idea, because you would be attempting to compare a solved floating point number with a floating point constant. You should never do equality checks on floating point numbers (in pretty much any language) and even more so when one of them is numerically solved. You should check within a tolerance. I would suggest either doing: Code:
i.e. give a tolerance on the comparison. Or maybe even: Code:
Note also that I changed the elseif to else if because that's also incorrect. I didn't check the correctness of the model itself. Looks simple enough. Regards, Andrew. |
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