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Design >> RF Design >> question on bandwith design in crystal osc
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Message started by microe on Feb 22^nd, 2010, 12:49pm

Title: question on bandwith design in crystal osc
Post by microe on Feb 22^nd, 2010, 12:49pm

Hello everyone,

I am designing a Pierce type crystal oscillator. It has has a amplitude control loop and a bias control loop (set the drain voltage, it is not a single resistor type of bias). The oscillation frequency is 10MHz. Target start up time is 200us (90% to final swing). One question I have is to design the bandwidth (3dB freq) of different loops.

To attenuate the AC signal, the bandwidth of the amplitude control loop (famp) has to be x200 smaller than fosc to have 46dB attenuation. That gives famp=50kHz

Assume the oscillation amplitude rising time is around 100us from 10% to 90%, that is equivalent of a bandwidth of around 3kHz. If we call it frise = 3kHz

Then the question is how to set the bandwidth of the DC bias loop. My thinking is it should be faster than frise because if the DC is not settled, the oscillation will not settle. It should be slower than the amp control loop so that both loops don't fight. So it should be around 15kHz.

Someone told me DC bias loop bandwidth should be smaller than frise. I don't understand why.

Any comments and suggestions are welcome.
Thanks.

Title: Re: question on bandwith design in crystal osc
Post by rfcooltools.com on Feb 23^rd, 2010, 12:13pm

These are rules of thumbs from circuit board implementation days.
Basically you don't want to kill the oscillation before it is fully stable.
See the back ground info below for a better understanding of some of the little known properties of crystals.
Here is what I would do:
If you are designing a oscillator on chip and logic circuits are relatively small, then I would suggest overriding the control loop with a switch until several clock pulses have been counted then release the control loop override switch. Or you could override the control loop for a given known period from some other source ie simple relaxation oscillator. Finally as an alternative you could give the crystal oscillator a good first kick to send the oscillation to steady state faster.

Back ground
Crystals often have a phenomenon called sleeping crystal where there are micro particles attached to the crystal physically. These micro particles dampen the crystal (like dust on the exterior of a pipe organ) and effectively lower the Q of the crystal prior to first oscillation or after a long period of non oscillation. Right After oscillation occurs the crystal shakes these particles loose and the Q of the crystal increases.

J

Title: Re: question on bandwith design in crystal osc
Post by microe on Feb 23^rd, 2010, 12:35pm

Thanks for your information.

It is an on-chip osc. We do have initial kicking to make the startup faster. What I'd like to know is how to decide the bandwidth of bias control loop, shall it be higher or lower than the bandwidth of the amplitude control loop? I am trying to setup simulations to see its effect.

Thanks.

Title: Re: question on bandwith design in crystal osc
Post by loose-electron on Feb 23^rd, 2010, 7:47pm

Crystal kicking does not work reliably and should not be used in a design.

Period.

No conditionals...

and yes, I know there are patents on the concept and people have "tried" to use it in products.... don't go there.

About 6 months back I ended up cleaning up a design for a product where they had attempted to use this. It doesn't work reliably.

Get the crystal Q, and look at the spectral response of that simplified model, trying to "kick" that works relaibly only on a simulator.

Title: Re: question on bandwith design in crystal osc
Post by microe on Feb 23^rd, 2010, 8:34pm

Thanks for your comment.

In my understanding, there are two ways to make startup faster: high negative R (high loop gain) and initial kicking. I understand kicking does not help much if the negative R is not high enough, since it cannot sustain the oscillation. But in the designs that the negative R is high enough, kicking should make the startup faster, isn't it?

loose-electron wrote on Feb 23^rd, 2010, 7:47pm:

Crystal kicking does not work reliably and should not be used in a design.

Period.

No conditionals...

...

Title: Re: question on bandwith design in crystal osc
Post by loose-electron on Feb 24^th, 2010, 6:26am

I dont have the numbers in front of me at the moment but --- the Q of a crystal is roughly 1E5 or 1E6.

Think of it as a very narrow BW bandpass filter.

To "kick" or stimulate that narrow a BW requires injecting a signal within a few Hz of accuracy.

Doesn't work in the real world, unless you already have a xtal running at that same frequency, and then, whats the point?

Suggest - look at a normal start crystal (slow rise yes) and provide a gain regulator and output buffer so that you use the output and stabilize the amplitude at a small signal out of the crystal, instead of waiting for te slow amplitude buildup.

Title: Re: question on bandwith design in crystal osc
Post by microe on Feb 24^th, 2010, 11:04am

You are right, given the high Q of the crystal, kicking will inject little energy to the crystal. Its function may be just to make the circuit startup faster (biasing built up faster).

I agree that buffer will give us rail to rail swing before the osc settles to its final swing.

Do you have any suggestion on my original question: the relationship between the bias control loop and the amp control loop? I am using NMOS biased with a current mirror instead of an inverter to generate the negative R. The bias control loop set the drain voltage.

Thanks.

Title: Re: question on bandwith design in crystal osc
Post by loose-electron on Feb 25^th, 2010, 5:39pm

The classic single inverter with a crystal around it does not have enough gain in some process corners, unless you push the size of the inverter up.

When you push the inverter size up to get the gain needed in all corners, the static current gets terrible in other corners.

Look at another gain amplifier configuration instead.

I really don't see any good reason to put the bias current of the system in a control loop. Fixed bias conditions should be fine, and you really should not need any other control loops.

It's an amplifier and a crystal, keep it simple.

If you need the faster start time, look into a buffer amplifier (outside the crystal loop) to get a usable signal faster. Depending on your needs you may not need any gain control in the feedback, just let the thing go nonlinear (the buffer gain system) as the crystal signal builds.

Title: Re: question on bandwith design in crystal osc
Post by wave on Mar 1^st, 2010, 1:26pm

I agree with Loose-E.
The AGC and Bias loop are basically the same thing in my experience; I can't see why you'd have a 2nd loop for the bias.

The start up time seems too aggressive for a standard Q crystal. The Q is usually the limiting factor, regardless of what current you burn.

Remember your pkg and PCB parasitics. They can and will kill you.

goodluck,
Wave 8-)

Title: Re: question on bandwith design in crystal osc
Post by rfcooltools.com on Mar 5^th, 2010, 11:08pm

Loose electron read this because you may not see the bullets you think you dodged! and reconsider the need to literally kick the dust of the crystal.

stated definition
Low-level nonlinearity is sometimes called
“sleeping sickness” or “second level of drive” Its cause is generally resonator surface condition, which can be controlled through design and
control of manufacturing processes.
found in->
http://www.mtronpti.com/pdf/contentmgmt/crystal_resonator_terminology.pdf

For more info on why
http://www.femto-st.fr/~salzenst/04EFTFbrendel.pdf

Title: Re: question on bandwith design in crystal osc
Post by loose-electron on Mar 8^th, 2010, 10:43am

"Loose electron read this because you may not see the bullets you think you dodged!"

Interesting read - however that's talking about the initial start of oscillation and my concern was more about a rapid starting by crystal kicking, and the Q of the crystal doesn't really allow that too well.

Dodge bullets? Hardly, its generally easier to take them in the chest! ;D

Title: Re: question on bandwith design in crystal osc
Post by rf-design on Mar 9^th, 2010, 1:17am

I do not understand the reason for having two control loops.

If the reason for the DC bias control loop is to improve startup and increase reliability the only way to derive a control signal is the amplitude themselve or using a counter. But the the counter solution is critical because you have to set the bias start value and final value. That places more risk on variability.

I have done some regulated NMOS and NPN based pierce oscillators in the last 20 years and found that the amplitude regulator need some filtering but the filtering needed for proper operation is surprising low. The remaining peak to peak versus avarage value of the bias current in the regulation loop could reach 30% w/o significant impact on frequency stability and and final amplitude. I design it in the range 3%-10% because there is some phase sensitivity of the bias current modulation to the effective Gm.

To loose-electron:

What the point of tuned kicking XTAL?

There is a big interest in doing that because startup reduction is critical in some radio applications. If the startup time is 100x the active time of a system it contribute significant to the energy budget. In terms of efficiency you want to operate the resonator with specific power level. That requires some energy stored in the reactances. The question is now how to pump the energy in so that the efficiency, reactance energy to DC energy, is high.
If you calculate the effciency you are right that efficiency is invers to the relative frequency difference. But there are kicking oscilators out there which are tuned to ppm and remain there over % of supply and slow temp changes.

Title: Re: question on bandwith design in crystal osc
Post by microe on Mar 9^th, 2010, 10:26am

Thanks for all the suggestions and comments.

Just to clarify one thing, when I say the bias loop, I mean the loop to sense the drain voltage and feedback to gate to make the transistor stays in saturation (DC wise). Usually this DC control is implemented through a simple resistor connecting gate and drain, like in Vittoz's paper. We are not using that because of power and swing.

Title: Re: question on bandwith design in crystal osc
Post by loose-electron on Mar 9^th, 2010, 2:03pm

[quote author=rf-design link=1266871751/0#11 date=1268126222
What the point of tuned kicking XTAL?
[/quote]

I am very aware of what people want to do with crystal kicking, and I have read some of the papers and patents on the subject. I have also designed enough RF front ends that wanted to be used in a time interleaved fashion and get things started up quickly is something I have had to deal with before.

However, I have also designed enough oscillators to know what works and what does not work.

More specific to crystal kicking, I have had my hands on a design in the lab and seen what happens, what the yield losses are.

They are unreliable, and have high yield losses because you cant "hit the kick frequency" with the needed accuracy.

If you can "crystal kick" with enough frequency accuracy to do something real towards speeding up the oscillation time, that means you already have an oscillator running with a well defined, highly accurate frequency.

If you got that, what need is there in starting up a second oscillator?

Even a tweaked and trimmed RC type oscillator will not be consistent enough to stimulate a crystal properly, thermal variance will make this drift out of band from the crystal. A tuned LC system will have a little better success but getting things aligned in frequency is a fussy prospect that is not viable in a volume product. Remember, the whole idea here is to create an accurate oscillation, and you don't have one readily available to work with.

I will come back to my original statement - If you want to get an oscillator up and running fast, look into running the device at lower amplitudes to avoid the slow ramp up in amplitude. There are also ways of running crystals at low amplitude, low power setups that can be kept running in the background and consume little power.

Title: Re: question on bandwith design in crystal osc
Post by rf-design on Mar 9^th, 2010, 2:34pm

An RC-oscillator inherit the 50-200ppm/K from the Poly-Res. The clear solution is to adjust the RC every RTC period and second to use the RC also as RTC. Because within the RTC periods the temp drift is very low. The only critical stuff was the initial tune in code and model detail for verification.

Title: Re: question on bandwith design in crystal osc
Post by loose-electron on Mar 10^th, 2010, 4:28pm

rf-design wrote on Mar 9^th, 2010, 2:34pm:

Sounds simple!

Now - go do something very quantitative:

1. Find the frequency accuracy needed to hit a tuned circuit (the crystal) with enough accuracy to realize less than 3dB-6dB of passband loss. The Q of your circuit is 0.5 x 10E6. For the sake of argument, lets call it a 10MHz crystal.

I expect you will find an answer that is under 50Hz, and if my memory serves me correctly the answer is around 20Hz.

2. Go model that RC oscillator, put in all the PVT corner variables and determine the frequency variance.

I expect you will find a +/- 40% variance (give or take)

3. Determine how much resolution you are going to need to get an adjust circuit that can be "tuned" within 1/2 of the tuned accuracy stated above. (best guess is 10Hz) - so with an RC oscillator that varies from 14MHz to 6MHz (delta = 8 MHz) your adjust system needs 800,000 adjustment points.

Thats a lot of tuning and adjustment to hit a very narrow frequency window.

Now, after you get that circuit tuned up to hit the right frequency, change something, pretty much anything, but lets say change the temperature, or the power supply voltage.

You just lost your tuning point, and you are outside the frequency window.

Your numbers may vary, but the above is the concept. Problems are seen in simulation, and I have seen this idea in the lab and seen that it has problems there too.

Title: Re: question on bandwith design in crystal osc
Post by rf-design on Mar 11^th, 2010, 1:41am

Jerry

it is interesting to meet the same project requirement a second time. As we both know about the difficult, but not unsolveable, specification for the tuned RTC-RC-oscillator regarding voltage sensitivity, temperature sensitivity and resolution I will add three further points.

1. Pressure sensitivity of the poly-poly-cap and pressure sensitivity of the poly-grain-resistance. Pressure comes through bend from board to package frame to die. Touching the package surface lead to the same effect but is more for diagnosis that the effect is in place as predicted.

2. Transient temperature changes in die. Beside that the project was a low power <30mW there where different activities in the die which lead to 2D transient temperature profiles. Floorplanning had to be optimized within this data.

3. <0.5K temperature cycling lead to hysteresis effects. It was expected to be proportional to the temperature cycle but not exactly to characterize.

The key to solve above further design road blocks was digital. The tuning code was made adaptive because if you hit not exactly the resonator simply the power efficiency goes down. There is no hard degradation. Only the RTC-burst protocol have to forsee this tuning result.

Title: Re: question on bandwith design in crystal osc
Post by loose-electron on Mar 12^th, 2010, 1:14pm

there is a much simpler solution and everyone seems to keep ignoring what I said originally -

put a lot of gain after the crystal oscillator so the signal is usable at a small amplitude and does not need to need to go thru the long period of start up amplitude growing.

that works. its simple and works reliably.