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Design >> Analog Design >> Parasitic & Floating Capacitance
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Message started by Asmodeus on Feb 24^th, 2010, 12:56am

Title: Parasitic & Floating Capacitance
Post by Asmodeus on Feb 24^th, 2010, 12:56am

Hi Guys,

I am looking for some numbers so as to get an idea of magnitude of top plate and bottom plate parasitic capacitance in MIMCAPs (data for other kind of capacitance implementation is also welcome ;-) ). Can this information be found in PDKs ?? Any paper on it is really welcome.

Second doubt i have got is suppose if i am having a floating capacitance in my circuit. How does it affect my circuit. Does it really affect. My thinking is that a floating capacitance is not really floating due to presence of the parasitic capacitances. Please comment on it.

Title: Re: Parasitic & Floating Capacitance
Post by vivkr on Feb 24^th, 2010, 1:56am

Asmodeus wrote on Feb 24^th, 2010, 12:56am:

Hi,

Usually MIM caps are made in relatively higher metal levels and both top and bottom plate parasitics are generally negligible (1-2%). Usually, this number should be in the process doc, but that depends on your foundry. Some may simply not specify it at all. What may be more relevant is parasitic capacitance to other nets running all around.

As to floating nets, one speaks of them as "floating" in a DC sense. This is not good because you may have coupling between a sensitive net and a noisy net through the capacitive bridge that the floating net provides. If the floating net is fairly large and tied to a gate, then you may have antenna problems during fabrication.

Vivek

Title: Re: Parasitic & Floating Capacitance
Post by ywguo on Feb 24^th, 2010, 9:09pm

Hi Asmodeus,

For example, one MIM cap, bottom plate is Metal 5. I check the operating point.
C_MIM=108.5fF, C_par=0.86fF.
As what Vivek said, it depends on your PDK and SPICE model. Some foundry don't invest enough source into PDK and SPICE model so that you cannot see this information.

Yawei