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Design Languages >> Verilog-AMS >> Arrays in verilog
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Message started by akhil on Mar 5^th, 2010, 9:37pm

Title: Arrays in verilog
Post by akhil on Mar 5^th, 2010, 9:37pm

Can we use double dimensional arrays in verilog ..
if so how ?

Title: Re: Arrays in verilog
Post by pancho_hideboo on Mar 6^th, 2010, 2:31am

Quote:

`define Nrow 4
`define Ncol 3

integer aaa[0:`Nrow*`Ncol-1];

"aaa[i][j]" can be accessed as "aaa[`Ncol*i+j], 0<=i<=`Nrow-1, 0<=j<=`Ncol-1".

Title: Re: Arrays in verilog
Post by akhil on Mar 6^th, 2010, 7:31am

Can we have double dimensional input output ports...

Title: Re: Arrays in verilog
Post by akhil on Mar 6^th, 2010, 7:54am

cud u xplain the above post...as i am a beginner ...i can see only 1 dimensional array

Title: Re: Arrays in verilog
Post by akhil on Mar 6^th, 2010, 10:03am

Actually i wanted to design 64 bit prefix adders..so while writing the verilog code i wrote
output [63:0] c [1:0] ;
as i wanted to store 64 propagate and generate functions ...i.e for each bit i would store the G and P ...
but it was throwing up error during compilatio

Secondly , can i get some web link where i can find more about prefix adders in terms of verilog code not the description part

Title: Re: Arrays in verilog
Post by Marq Kole on Mar 8^th, 2010, 7:02am

As far as I know Verilog IEEE 1364-2008 only supports one-dimensional arrays. SystemVerilog IEEE 1800-2009 does have multi-dimensional array support.

Cheers,
Marq