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Design Languages >> Verilog-AMS >> Clock speed change
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Message started by JrWin on Mar 7^th, 2010, 6:47pm

Title: Clock speed change
Post by JrWin on Mar 7^th, 2010, 6:47pm

Hi,

I am working on a CPLD project. The program was originally sending 8-bits data in parallel. Now I have to change it to send the data in serial.

So the clock speed was set to 8 times faster. But the problem is that the
data still have to be read from the buffer in parallel before sending.

The original coding for the parallel data output is as following:

Code:

always @ (iPSClk) // clock for parallel data output
begin
if(iPSClk)
oRead = 0; // triggers read at the falling edge;
else
oRead = 1;
end

Then it was modified for the serial output:

Code:

always @(rBitCnt)
begin
if((rBitCnt == 4) || (rBitCnt == 5) || (rBitCnt == 6) || (rBitCnt == 7))
oRead = 0;
else
oRead = 1;
end

always @(negedge iPSClk2) // new clock for serial output
begin
if(rBitCnt < 7)
rBitCnt = rBitCnt + 1;
else
rBitCnt = 0;
end

The oRead signals measured by the analyzer are in the same timing, however, the program is not working.

So it will be great help, if anyone knows better ways to remain the oRead timing with new faster clock.

Thank you,
JR

Title: Re: Clock speed change
Post by Marq Kole on Mar 8^th, 2010, 7:03am

Hi,

This is the section for Verilog-AMS, so that's the mixed-signal extensions to Verilog. Although Verilog 1364-2008 is a full subset of the Verilog-AMS 2.3.1 language, I think you will find that the people that could answer your question normally do not visit this forum.

Cheers,
Marq