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Design Languages >> Verilog-AMS >> how to set up a time variable resistor model?
https://designers-guide.org/forum/YaBB.pl?num=1268085149

Message started by liletian on Mar 8^th, 2010, 1:52pm

Title: how to set up a time variable resistor model?
Post by liletian on Mar 8^th, 2010, 1:52pm

Hi All
Does any of you know how to build a time variable resistor model.
I used the following verilogA code, but I can not use $time in my code. Does anyone know if there is a way to do it?
Thank you
// VerilogA for verilogA_lib, res, veriloga

`include "constants.vams"
`include "disciplines.vams"

module res(p,n);
inout p,n;
electrical p,n;
parameter real r=0 from [0:inf);V(p,n) <+($time+ r)*I(p,n); Does not work at all

endmodule

Title: Re: how to set up a time variable resistor model?
Post by Andrew Beckett on Mar 8^th, 2010, 2:00pm

You'd need to use $abstime, not $time. $time is not supported in an analog context (see the LRM; links from the Verilog-AMS link at the top of the page).

Regards,

Andrew.

Title: Re: how to set up a time variable resistor model?
Post by liletian on Mar 9^th, 2010, 1:16pm

Andrew Beckett wrote on Mar 8^th, 2010, 2:00pm:

You'd need to use $abstime, not $time. $time is not supported in an analog context (see the LRM; links from the Verilog-AMS link at the top of the page).

Regards,

Andrew.

thank you very much, it is really helpful.