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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Increase veriloga simulation accuracy in hspice simulator https://designers-guide.org/forum/YaBB.pl?num=1268085833 Message started by neoflash on Mar 8th, 2010, 2:03pm |
Title: Increase veriloga simulation accuracy in hspice simulator Post by neoflash on Mar 8th, 2010, 2:03pm Hi, I found even if I specify hspice accuracy setting to runlvl=6 and accurate, the waveform from verilogA blocks still look ugly. Is there any other setting I can use to make verilogA part more accurate? Thanks, Neo |
Title: Re: Increase veriloga simulation accuracy in hspice simulator Post by patrick on Mar 8th, 2010, 4:35pm Try runlvl=0, i.e. disable runlvl. |
Title: Re: Increase veriloga simulation accuracy in hspice simulator Post by Geoffrey_Coram on Mar 10th, 2010, 7:15am You may also want to have a close look at your Verilog-A module: - does it have continuous/smooth outputs (as a function of the inputs) - do you have scaling issues (outputs that are huge or tiny compared to the normal scale of voltages and currents) |
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