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Design >> Mixed-Signal Design >> How to model the LC filter output impedance for ADC test
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Message started by roland on Mar 8^th, 2010, 7:49pm

Title: How to model the LC filter output impedance for ADC test
Post by roland on Mar 8^th, 2010, 7:49pm

Hi guys,
In the ADC test, we found the offchip stand-alone LC filter has large output impedance which makes the sampling path hard to settle well during the tracking phase. Do you have any idea about how to model the signal source impedance including the high-oder LC filters?

Title: Re: How to model the LC filter output impedance for ADC test
Post by rf-design on Mar 9^th, 2010, 1:32am

I think modelling could mean two approaches.

1. Modelling the charge kickback effect of the sampling cap
2. IIR discrete time modeling of this effect for the total transfer function

The first modelling simple. Use a ideal switch which is periodically connected to the LC filter output. The interesting point is now what happen to the sampling cap in the discharge phase. Is the cap discharged to zero or a quantized value or some other think. That determine the amount of charge flowing into the LC filter. And finally the IIR effect.

The IIR effect modelling guess a linear effect of the previous samples to actual sample. So it is like a discrete time filter on the toatl response. The aliasing rejection is not affacted by this effect. So if you can compensate or allow this linear filter effect you can avoid the buffer. But there are also voltage depend caps of the switch and switch parasitics. These lead to nonlinear effects if the source impedance is not very low and doe not have long time constants.

In high resolution, high speed pipeline ADC's the buffer often limit the performance. Some designs put a SiGe BiCMOS for the buffer on top of a CMOS ADC die.

Title: Re: How to model the LC filter output impedance for ADC test
Post by roland on Mar 10^th, 2010, 5:29pm

Hi Reiner,
Thanks! Your advice is really close to our thought. The IIR model was suggested in many papers. And the V-dependent parasitic cap in the switch is also what we concerned a lot. High source impedence, indeed, put some limitation on the switch size. However the source impedence is even higher than our estimation due to the LC filter, and unfortunately we do not employ a reset phase of the sampling cap.
We find it hard to model the commercial LC filter since it's a black box to us. Is it pratical to scan the output impedence of the filter first and build a verilog-a model? Or is there any simple empirical LC model for reference?

rf-design wrote on Mar 9^th, 2010, 1:32am:

Title: Re: How to model the LC filter output impedance for ADC test
Post by rf-design on Mar 11^th, 2010, 2:05am

Hi Roland,

I assume that the black box filter is a passive LC lowpass filter with specific termination impedances on both sides.

If that is the case the most efficient way to get a model which serve to aid your design process of the ADC is to replicate the LC ladder network. I found over years the tool FilterSolution most useful for design. If you know something about the filter I guess that the LC component values are not far away from the blackbox. You do not need a Verilog-A-code other than to implement a complete filter synthesis as higher level description. The issue with S-functions in Verilog-A is that the general implementation strategy of rational S-functions in the time domain does not inherit the sensitivity and stability properties of ladder designs. If you simulate with many switches in ADC with a high ratio of maximum to minimum variable time step the rational S-function could reduce the simulation performance.