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Design >> Analog Design >> PMOS switch bulk connection
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Message started by swolf on Mar 9^th, 2010, 4:12pm

Title: PMOS switch bulk connection
Post by swolf on Mar 9^th, 2010, 4:12pm

hi all

I have a problem when I design a sampling circuit. The sampling cap is very big, so the switch (which is a CMOS switch) resistance should be very low to get a good sampling presicion. but the PMOS size is very big to get a low resistance.

The bootstapped switch is not suitable because there are a lot of capacitors.

Normally, the PMOS bulk is connected to the VDD.
How about it if I connect the bulk of PMOS to its source to lower its Vth so the PMOS size could be smaller? I saw it in some paper which said that the bulk is connected to its source when it is in sampling phase and to Vdd when in hold phase.

I am not sure about it. Can anyone give me some hints? Thank you very much.

Title: Re: PMOS switch bulk connection
Post by tzg6sa on Mar 9^th, 2010, 5:10pm

Just make sure, that the drain voltage is less than the source's voltage (=bulk voltage)

Title: Re: PMOS switch bulk connection
Post by Berti on Mar 9^th, 2010, 11:23pm

Very big and very low doesn't sound very scientific ;)
Probably people will propose a better solution if they had some rough numbers...

Title: Re: PMOS switch bulk connection
Post by vivkr on Mar 10^th, 2010, 3:18am

agree with Berti.

By the way, that thing you are trying to make with a switch for the bulk is called a well switch and is a rather nasty thing to try and design, especially if you don't really need it. And believe me, you don't want to be in a position where you need it badly. A slight flaw in design, and you will latch your chip well and good.

It is also quite slow in operation and so I can hardly imagine that it would be well-suited to use in a high-speed sampling application.

I would recommend first optimizing the remaining stuff you have, trying to reduce the caps, trying to work out how large the on-resistance of the switches can be made and so on, and if you figure out that you don't need a well switch, then go with an NMOS switch instead of a PMOS.

Vivek

Title: Re: PMOS switch bulk connection
Post by swolf on Mar 10^th, 2010, 7:05am

Thanks to all !
What I am designing is a high resolution SAR ADC, which need a capacitor array. The voltage range of the input signal is from 0 to VDD. What I face is: with such big voltage range, a high resolution signal should be settling on the big capacitor array in about 1 us. I did the simulation and found the resistance of the switch should be about 40 ohm to meet the linerarity.
The technique I refered above is also called bulk switching. I saw it in some jssc papers and in some patent (from Broadcom). So I am confused. Do you have any good way to reduce the pmos size?
thank you very much!

Title: Re: PMOS switch bulk connection
Post by loose-electron on Mar 10^th, 2010, 4:35pm

clock bootstrapping a NMOS switch would be my preferred approach.

What's sizing your hold capacitor? KT/C issues?

Title: Re: PMOS switch bulk connection
Post by vivkr on Mar 12^th, 2010, 1:18am

I don't know about what patent that might be but well switching is a technique used very often in special applications, mainly in high-voltage circuits and so on, and usually slow enough that you could not use it well in a high-speed sampling application. Not that you cannot give it a shot for you application. If you have papers etc. which show how to do it fast, you can give it a try.

However, I would go with NMOS switch+bootstrapping, and first figure out how to reduce the caps as much as possible. If you can squeeze those down, then maybe you can even use standard transmission gates which would be much more compact in size even though they may be more nonlinear => tradeoff to be made here.

Vivek

Title: Re: PMOS switch bulk connection
Post by swolf on Mar 13^th, 2010, 4:58am

Thank you!

yes, the capacitance is limited by kt/C noise. bootstrap switch is a good method if there are only a few caps, but there are a lot of caps in the cap array (it consists of caps with capacitance as Cu, 2Cu, 4Cu, 8Cu…… )of my adc, so the bootstrap switches will occupy larger area than cmos switch do.

vivhr, I will take a simulation in detail on the speed as you referred. Thank you.

Title: Re: PMOS switch bulk connection
Post by Berti on Mar 15^th, 2010, 1:00am

You can use a single bootstrap circuitry to control several switches with the same phase.

Cheers

Title: Re: PMOS switch bulk connection
Post by rfmems on Mar 15^th, 2010, 6:34am

vivkr wrote on Mar 10^th, 2010, 3:18am:

A slight flaw in design, and you will latch your chip well and good.

Hi Vivek, could you please explain a bit how it will happen? Thanks.

Title: Re: PMOS switch bulk connection
Post by loose-electron on Mar 15^th, 2010, 3:00pm

if you are switching a binary weighted capacitor array in a dynamic manner you may want to consider some alternative architectures.

Title: Re: PMOS switch bulk connection
Post by vivkr on Mar 16^th, 2010, 3:07am

rfmems wrote on Mar 15^th, 2010, 6:34am:

vivkr wrote on Mar 10^th, 2010, 3:18am:

A slight flaw in design, and you will latch your chip well and good.

Hi Vivek, could you please explain a bit how it will happen? Thanks.

If you do not design your well switch properly, then you may end up forward biasing the diode to the well significantly during transients and inject significant current, which may then trigger parasitic bipolar transistors in the substrate. That is the usual latchup mechanism.

Vivek

Title: Re: PMOS switch bulk connection
Post by Asmodeus on Mar 24^th, 2010, 5:50am

One thing i want to add here is that u have to use a TG. Only NMOS n POMS won't work if ur input swing is 0-VDD.

Other than that u cn give more time 4 sampling, provided u r not making a high MSPS ADC, to get away 4m Non-Linearity !!

Title: Re: PMOS switch bulk connection
Post by swolf on Jun 29^th, 2010, 8:49pm

thank you all!

I found that the bulk switching technique is not very good, because this technique just promote a little of the performance.

the biggest problem with the CMOS switch (or TG) is the parasitic cap, which contribute to the input capacitance of the ADC. for example, the parasitic cap of a CMOS switch is 200fF while the correponding sampling cap is just 100 fF. So with 25.6 pF samling cap (determined by KT/C noise), the corresponding parasitic cap is about 50 pf, then the total input cap is about 75 pF!

Normally, the input cap is just 30 pF in the company product datasheet of the 16 bit or higher resolutio ADCs. It really confuses me. How to realize it? can anyone give me some suggestion?

loose-electron wrote on Mar 15^th, 2010, 3:00pm:

if you are switching a binary weighted capacitor array in a dynamic manner you may want to consider some alternative architectures.

Hi, loose-electron
Can you give me some advices? thank you!

Title: Re: PMOS switch bulk connection
Post by Mayank on Jun 29^th, 2010, 8:58pm

Quote:

So with 25.6 pF samling cap (determined by KT/C noise), the corresponding parasitic cap is about 50 pf

Why does parasitic cap has to increase to keep kT/C noise in control ?

CMOS TG will offer some resistance & parasitic cap. Let is stay 200f as it was earlier. The sampling cap of 25.6 pF at output node of TG will automaticall bring down kT/C noise to your calculated values.

Also, Binary weighted switching is more error prone. Like while switching from 0111 to 1000. All bits need to change. But if they dont change simultaneously, you might get an intermediate state like 1111 or 0000.
This will produce major glitches, esp. at factors of 2, resulting in spikes at these values in DNL response i guess. -- > SFDR degraded.

Title: Re: PMOS switch bulk connection
Post by swolf on Jun 30^th, 2010, 2:44am

hi, Mayank, thank you for your reply.
the LSB CAP with the size of one unit cap (100fF) needs a CMOS switch of a specific size, whose parasitic cap is 200fF; the second weighted CAP with the size of two unit cap needs two such CMOS switches to keep the linearity, so the parasitic cap is doubled.
That is, 100fF Sampling Cap corresponds to 200fF parasitic cap.

hi, Berti
I adopted this technique in pipeline ADC. But ...
Initially, I didn't want to use bootstrap switch here because there are so many switches. Now, it seems that I have to use this technique.
But I am still not very sure about it. Do you ever use this technique in this situation? any suggestion? Thank you.

Title: Re: PMOS switch bulk connection
Post by Asmodeus on Jun 30^th, 2010, 4:17am

From the above discussions, i guess u r sampling the input at the bottom plate of the DAC.

Are u using any buffer to drive the DAC ?? If not that could be an issue here. A rail-2-rail sample and hold usually needa a buffer to drive large DAC. Parasitic capacitance is not a big issue in the design of SAR ADCs, if it doesn't take part in charge redistribution.

Then 200fF parasitic capacitance seems a very big number for me for 100fF capacitance to settle in 1us. I will really ask you to look into the numbers once again :) Which technology node r u using ??

U can also design switch taking into consideration the effect parasitics added by it into settling consideration. Just make sure accessible node of parasitic capacitance is always at ac ground during charge redistribution. All u need to worry about is driving this total capacitance during sampling operation which will ask for a buffer.

Title: Re: PMOS switch bulk connection
Post by swolf on Jun 30^th, 2010, 8:25am

Hi, Asmodeus
yes, I used the bottom plate sampling technique.

About the CMOS switch, for example, the size of one unit switch is: NMOS: 15u/0.35u, PMOS: 55u/0.3u. The total gate area is about 20 um^2, and Cox=10 fF/um^2, so the total parasitic cap is 20*10=200 fF.
The linearity will not satisfy the SFDR performance if the size of switch get smaller.